--- trunk/src/memory_rw.c	2007/10/08 16:18:27	10
+++ trunk/src/memory_rw.c	2007/10/08 16:22:11	40
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: memory_rw.c,v 1.38 2005/06/27 07:03:39 debug Exp $
+ *  $Id: memory_rw.c,v 1.102 2007/04/16 15:13:44 debug Exp $
  *
  *  Generic memory_rw(), with special hacks for specific CPU families.
  *
@@ -48,15 +48,11 @@
  *			a placeholder for data when reading from memory
  *	len		the length of the 'data' buffer
  *	writeflag	set to MEM_READ or MEM_WRITE
- *	cache_flags	CACHE_{NONE,DATA,INSTRUCTION} | other flags
+ *	misc_flags	CACHE_{NONE,DATA,INSTRUCTION} | other flags
  *
  *  If the address indicates access to a memory mapped device, that device'
  *  read/write access function is called.
  *
- *  If instruction latency/delay support is enabled, then
- *  cpu->instruction_delay is increased by the number of instruction to
- *  delay execution.
- *
  *  This function should not be called with cpu == NULL.
  *
  *  Returns one of the following:
@@ -66,222 +62,73 @@
  *  (MEMORY_ACCESS_FAILED is 0.)
  */
 int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
-	unsigned char *data, size_t len, int writeflag, int cache_flags)
+	unsigned char *data, size_t len, int writeflag, int misc_flags)
 {
+#ifdef MEM_ALPHA
+	const int offset_mask = 0x1fff;
+#else
+	const int offset_mask = 0xfff;
+#endif
+
 #ifndef MEM_USERLAND
 	int ok = 1;
 #endif
 	uint64_t paddr;
 	int cache, no_exceptions, offset;
 	unsigned char *memblock;
-#ifdef BINTRANS
-	int bintrans_cached = cpu->machine->bintrans_enable;
-	int bintrans_device_danger = 0;
-#endif
-	no_exceptions = cache_flags & NO_EXCEPTIONS;
-	cache = cache_flags & CACHE_FLAGS_MASK;
-
-#ifdef MEM_PPC
-	if (cpu->cd.ppc.bits == 32)
-		vaddr &= 0xffffffff;
-#endif
+	int dyntrans_device_danger = 0;
 
-#ifdef MEM_ARM
-	vaddr &= 0x3fffffff;
-#endif
+	no_exceptions = misc_flags & NO_EXCEPTIONS;
+	cache = misc_flags & CACHE_FLAGS_MASK;
 
-#ifdef MEM_X86
-	/*  Real-mode wrap-around:  */
-	if (REAL_MODE && !(cache_flags & PHYSICAL)) {
-		if ((vaddr & 0xffff) + len > 0x10000) {
-			/*  Do one byte at a time:  */
-			int res = 0, i;
-			for (i=0; i<len; i++)
-				res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1,
-				    writeflag, cache_flags);
-			return res;
-		}
-	}
-
-	/*  Crossing a page boundary? Then do one byte at a time:  */
-	if ((vaddr & 0xfff) + len > 0x1000 && !(cache_flags & PHYSICAL)
-	    && cpu->cd.x86.cr[0] & X86_CR0_PG) {
-		/*  For WRITES: Read ALL BYTES FIRST and write them back!!!
-		    Then do a write of all the new bytes. This is to make sure
-		    than both pages around the boundary are writable so we don't
-		    do a partial write.  */
-		int res = 0, i;
-		if (writeflag == MEM_WRITE) {
-			unsigned char tmp;
-			for (i=0; i<len; i++) {
-				res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1,
-				    MEM_READ, cache_flags);
-				if (!res)
-					return 0;
-				res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1,
-				    MEM_WRITE, cache_flags);
-				if (!res)
-					return 0;
-			}
-			for (i=0; i<len; i++) {
-				res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1,
-				    MEM_WRITE, cache_flags);
-				if (!res)
-					return 0;
-			}
-		} else {
-			for (i=0; i<len; i++) {
-				/*  Do one byte at a time:  */
-				res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1,
-				    writeflag, cache_flags);
-				if (!res) {
-					if (cache == CACHE_INSTRUCTION) {
-						fatal("FAILED instruction "
-						    "fetch across page boundar"
-						    "y: todo. vaddr=0x%08x\n",
-						    (int)vaddr);
-						cpu->running = 0;
-					}
-					return 0;
-				}
-			}
-		}
-		return res;
-	}
-#endif	/*  X86  */
-
-#ifdef MEM_URISC
-	{
-		uint64_t mask = (uint64_t) -1;
-		if (cpu->cd.urisc.wordlen < 64)
-			mask = ((int64_t)1 << cpu->cd.urisc.wordlen) - 1;
-		vaddr &= mask;
-	}
-#endif
-
-#ifdef MEM_MIPS
-#ifdef BINTRANS
-	if (bintrans_cached) {
-		if (cache == CACHE_INSTRUCTION) {
-			cpu->cd.mips.pc_bintrans_host_4kpage = NULL;
-			cpu->cd.mips.pc_bintrans_paddr_valid = 0;
-		}
-	}
-#endif
-#endif	/*  MEM_MIPS  */
 
 #ifdef MEM_USERLAND
+#ifdef MEM_ALPHA
+	paddr = vaddr;
+#else
 	paddr = vaddr & 0x7fffffff;
-	goto have_paddr;
 #endif
-
-#ifndef MEM_USERLAND
-#ifdef MEM_MIPS
-	/*
-	 *  For instruction fetch, are we on the same page as the last
-	 *  instruction we fetched?
-	 *
-	 *  NOTE: There's no need to check this stuff here if this address
-	 *  is known to be in host ram, as it's done at instruction fetch
-	 *  time in cpu.c!  Only check if _host_4k_page == NULL.
-	 */
-	if (cache == CACHE_INSTRUCTION &&
-	    cpu->cd.mips.pc_last_host_4k_page == NULL &&
-	    (vaddr & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) {
-		paddr = cpu->cd.mips.pc_last_physical_page | (vaddr & 0xfff);
-		goto have_paddr;
-	}
-#endif	/*  MEM_MIPS  */
-
-	if (cache_flags & PHYSICAL || cpu->translate_address == NULL) {
+#else	/*  !MEM_USERLAND  */
+	if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) {
 		paddr = vaddr;
 	} else {
-		ok = cpu->translate_address(cpu, vaddr, &paddr,
+		ok = cpu->translate_v2p(cpu, vaddr, &paddr,
 		    (writeflag? FLAG_WRITEFLAG : 0) +
 		    (no_exceptions? FLAG_NOEXCEPTIONS : 0)
-#ifdef MEM_X86
-		    + (cache_flags & NO_SEGMENTATION)
+#ifdef MEM_ARM
+		    + (misc_flags & MEMORY_USER_ACCESS)
 #endif
 		    + (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0));
-		/*  If the translation caused an exception, or was invalid in
-		    some way, we simply return without doing the memory
-		    access:  */
+
+		/*
+		 *  If the translation caused an exception, or was invalid in
+		 *  some way, then simply return without doing the memory
+		 *  access:
+		 */
 		if (!ok)
 			return MEMORY_ACCESS_FAILED;
 	}
 
-
-#ifdef MEM_X86
-	/*  DOS debugging :-)  */
-	if (!quiet_mode && !(cache_flags & PHYSICAL)) {
-		if (paddr >= 0x400 && paddr <= 0x4ff)
-			debug("{ PC BIOS DATA AREA: %s 0x%x }\n", writeflag ==
-			    MEM_WRITE? "writing to" : "reading from",
-			    (int)paddr);
-#if 0
-		if (paddr >= 0xf0000 && paddr <= 0xfffff)
-			debug("{ BIOS ACCESS: %s 0x%x }\n",
-			    writeflag == MEM_WRITE? "writing to" :
-			    "reading from", (int)paddr);
-#endif
-	}
-#endif
-
-#ifdef MEM_MIPS
-	/*
-	 *  If correct cache emulation is enabled, and we need to simluate
-	 *  cache misses even from the instruction cache, we can't run directly
-	 *  from a host page. :-/
-	 */
-#if defined(ENABLE_CACHE_EMULATION) && defined(ENABLE_INSTRUCTION_DELAYS)
-#else
-	if (cache == CACHE_INSTRUCTION) {
-		cpu->cd.mips.pc_last_virtual_page = vaddr & ~0xfff;
-		cpu->cd.mips.pc_last_physical_page = paddr & ~0xfff;
-		cpu->cd.mips.pc_last_host_4k_page = NULL;
-
-		/*  _last_host_4k_page will be set to 1 further down,
-		    if the page is actually in host ram  */
-	}
-#endif
-#endif	/*  MEM_MIPS  */
-#endif	/*  ifndef MEM_USERLAND  */
-
-
-#if defined(MEM_MIPS) || defined(MEM_USERLAND)
-have_paddr:
-#endif
-
-
-#ifdef MEM_MIPS
-	/*  TODO: How about bintrans vs cache emulation?  */
-#ifdef BINTRANS
-	if (bintrans_cached) {
-		if (cache == CACHE_INSTRUCTION) {
-			cpu->cd.mips.pc_bintrans_paddr_valid = 1;
-			cpu->cd.mips.pc_bintrans_paddr = paddr;
-		}
-	}
-#endif
-#endif	/*  MEM_MIPS  */
-
+#endif	/*  !MEM_USERLAND  */
 
 
 #ifndef MEM_USERLAND
 	/*
 	 *  Memory mapped device?
 	 *
-	 *  TODO: this is utterly slow.
-	 *  TODO2: if paddr<base, but len enough, then we should write
-	 *  to a device to
+	 *  TODO: if paddr < base, but len enough, then the device should
+	 *  still be written to!
 	 */
 	if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) {
-#ifdef BINTRANS
 		uint64_t orig_paddr = paddr;
-#endif
-		int i, start, res;
+		int i, start, end, res;
+
+#if 0
+
+TODO: The correct solution for this is to add RAM devices _around_ the
+dangerous device. The solution below incurs a slowdown for _everything_,
+not just the device in question.
 
-#ifdef BINTRANS
 		/*
 		 *  Really really slow, but unfortunately necessary. This is
 		 *  to avoid the folowing scenario:
@@ -290,88 +137,97 @@
 		 *	b) offsets 0x124..0x777 are a device
 		 *
 		 *	1) a read is done from offset 0x100. the page is
-		 *	   added to the bintrans system as a "RAM" page
-		 *	2) a bintranslated read is done from offset 0x200,
+		 *	   added to the dyntrans system as a "RAM" page
+		 *	2) a dyntranslated read is done from offset 0x200,
 		 *	   which should access the device, but since the
 		 *	   entire page is added, it will access non-existant
 		 *	   RAM instead, without warning.
 		 *
-		 *  Setting bintrans_device_danger = 1 on accesses which are
+		 *  Setting dyntrans_device_danger = 1 on accesses which are
 		 *  on _any_ offset on pages that are device mapped avoids
 		 *  this problem, but it is probably not very fast.
+		 *
+		 *  TODO: Convert this into a quick (multi-level, 64-bit)
+		 *  address space lookup, to find dangerous pages.
 		 */
-		if (bintrans_cached) {
-			for (i=0; i<mem->n_mmapped_devices; i++)
-				if (paddr >= (mem->dev_baseaddr[i] & ~0xfff) &&
-				    paddr <= ((mem->dev_baseaddr[i] +
-				    mem->dev_length[i] - 1) | 0xfff)) {
-					bintrans_device_danger = 1;
-					break;
-				}
-		}
+		for (i=0; i<mem->n_mmapped_devices; i++)
+			if (paddr >= (mem->devices[i].baseaddr & ~offset_mask)&&
+			    paddr <= ((mem->devices[i].endaddr-1)|offset_mask)){
+				dyntrans_device_danger = 1;
+				break;
+			}
 #endif
 
-		i = start = mem->last_accessed_device;
+		start = 0; end = mem->n_mmapped_devices - 1;
+		i = mem->last_accessed_device;
 
 		/*  Scan through all devices:  */
 		do {
-			if (paddr >= mem->dev_baseaddr[i] &&
-			    paddr < mem->dev_baseaddr[i] + mem->dev_length[i]) {
+			if (paddr >= mem->devices[i].baseaddr &&
+			    paddr < mem->devices[i].endaddr) {
 				/*  Found a device, let's access it:  */
 				mem->last_accessed_device = i;
 
-				paddr -= mem->dev_baseaddr[i];
-				if (paddr + len > mem->dev_length[i])
-					len = mem->dev_length[i] - paddr;
-
-#ifdef BINTRANS
-				if (bintrans_cached && mem->dev_flags[i] &
-				    MEM_BINTRANS_OK) {
+				paddr -= mem->devices[i].baseaddr;
+				if (paddr + len > mem->devices[i].length)
+					len = mem->devices[i].length - paddr;
+
+				if (cpu->update_translation_table != NULL &&
+				    !(ok & MEMORY_NOT_FULL_PAGE) &&
+				    mem->devices[i].flags & DM_DYNTRANS_OK) {
 					int wf = writeflag == MEM_WRITE? 1 : 0;
+					unsigned char *host_addr;
 
-					if (writeflag) {
-						if (paddr < mem->
-						    dev_bintrans_write_low[i])
-							mem->
-							dev_bintrans_write_low
-							    [i] =
-							    paddr & ~0xfff;
-						if (paddr > mem->
-						    dev_bintrans_write_high[i])
-							mem->
-						 	dev_bintrans_write_high
-							    [i] = paddr | 0xfff;
+					if (!(mem->devices[i].flags &
+					    DM_DYNTRANS_WRITE_OK))
+						wf = 0;
+
+					if (writeflag && wf) {
+						if (paddr < mem->devices[i].
+						    dyntrans_write_low)
+							mem->devices[i].
+							dyntrans_write_low =
+							    paddr &~offset_mask;
+						if (paddr >= mem->devices[i].
+						    dyntrans_write_high)
+							mem->devices[i].
+						 	dyntrans_write_high =
+							    paddr | offset_mask;
 					}
 
-					if (!(mem->dev_flags[i] &
-					    MEM_BINTRANS_WRITE_OK))
-						wf = 0;
+					if (mem->devices[i].flags &
+					    DM_EMULATED_RAM) {
+						/*  MEM_WRITE to force the page
+						    to be allocated, if it
+						    wasn't already  */
+						uint64_t *pp = (uint64_t *)mem->
+						    devices[i].dyntrans_data;
+						uint64_t p = orig_paddr - *pp;
+						host_addr =
+						    memory_paddr_to_hostaddr(
+						    mem, p & ~offset_mask,
+						    MEM_WRITE);
+					} else {
+						host_addr = mem->devices[i].
+						    dyntrans_data +
+						    (paddr & ~offset_mask);
+					}
 
-					update_translation_table(cpu,
-					    vaddr & ~0xfff,
-					    mem->dev_bintrans_data[i] +
-					    (paddr & ~0xfff),
-					    wf, orig_paddr & ~0xfff);
+					cpu->update_translation_table(cpu,
+					    vaddr & ~offset_mask, host_addr,
+					    wf, orig_paddr & ~offset_mask);
 				}
-#endif
 
 				res = 0;
-				if (!no_exceptions || (mem->dev_flags[i] &
-				    MEM_READING_HAS_NO_SIDE_EFFECTS))
-					res = mem->dev_f[i](cpu, mem, paddr,
+				if (!no_exceptions || (mem->devices[i].flags &
+				    DM_READS_HAVE_NO_SIDE_EFFECTS))
+					res = mem->devices[i].f(cpu, mem, paddr,
 					    data, len, writeflag,
-					    mem->dev_extra[i]);
+					    mem->devices[i].extra);
 
-#ifdef ENABLE_INSTRUCTION_DELAYS
 				if (res == 0)
 					res = -1;
 
-				cpu->cd.mips.instruction_delay +=
-				    ( (abs(res) - 1) *
-				     cpu->cd.mips.cpu_type.instrs_per_cycle );
-#endif
-
-#ifndef MEM_X86
 				/*
 				 *  If accessing the memory mapped device
 				 *  failed, then return with a DBE exception.
@@ -380,21 +236,22 @@
 					debug("%s device '%s' addr %08lx "
 					    "failed\n", writeflag?
 					    "writing to" : "reading from",
-					    mem->dev_name[i], (long)paddr);
+					    mem->devices[i].name, (long)paddr);
 #ifdef MEM_MIPS
 					mips_cpu_exception(cpu, EXCEPTION_DBE,
 					    0, vaddr, 0, 0, 0, 0);
 #endif
 					return MEMORY_ACCESS_FAILED;
 				}
-#endif
 				goto do_return_ok;
 			}
 
-			i ++;
-			if (i == mem->n_mmapped_devices)
-				i = 0;
-		} while (i != start);
+			if (paddr < mem->devices[i].baseaddr)
+				end = i - 1;
+			if (paddr >= mem->devices[i].endaddr)
+				start = i + 1;
+			i = (start + end) >> 1;
+		} while (start <= end);
 	}
 
 
@@ -406,7 +263,7 @@
 	switch (cpu->cd.mips.cpu_type.mmu_model) {
 	case MMU3K:
 		/*  if not uncached addess  (TODO: generalize this)  */
-		if (!(cache_flags & PHYSICAL) && cache != CACHE_NONE &&
+		if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE &&
 		    !((vaddr & 0xffffffffULL) >= 0xa0000000ULL &&
 		      (vaddr & 0xffffffffULL) <= 0xbfffffffULL)) {
 			if (memory_cache_R3000(cpu, cache, paddr,
@@ -414,33 +271,6 @@
 				goto do_return_ok;
 		}
 		break;
-#if 0
-/*  Remove this, it doesn't work anyway  */
-	case MMU10K:
-		/*  other cpus:  */
-		/*
-		 *  SUPER-UGLY HACK for SGI-IP32 PROM, R10000:
-		 *  K0 bits == 0x3 means uncached...
-		 *
-		 *  It seems that during bootup, the SGI-IP32 prom
-		 *  stores a return pointers a 0x80000f10, then tests
-		 *  memory by writing bit patterns to 0xa0000xxx, and
-		 *  then when it's done, reads back the return pointer
-		 *  from 0x80000f10.
-		 *
-		 *  I need to find the correct way to disconnect the
-		 *  cache from the main memory for R10000.  (TODO !!!)
-		 */
-/*		if ((cpu->cd.mips.coproc[0]->reg[COP0_CONFIG] & 7) == 3) {  */
-/*
-		if (cache == CACHE_DATA &&
-		    cpu->r10k_cache_disable_TODO) {
-			paddr &= ((512*1024)-1);
-			paddr += 512*1024;
-		}
-*/
-		break;
-#endif
 	default:
 		/*  R4000 etc  */
 		/*  TODO  */
@@ -463,76 +293,13 @@
 		} else
 #endif /* MIPS */
 		{
-			if (paddr >= mem->physical_max) {
-				char *symbol;
-#ifdef MEM_MIPS
-				uint64_t offset;
-#endif
-				/*  This allows for example OS kernels to probe
-				    memory a few KBs past the end of memory,
-				    without giving too many warnings.  */
-				if (!quiet_mode && paddr >=
-				    mem->physical_max + 0x40000) {
-					fatal("[ memory_rw(): writeflag=%i ",
-					    writeflag);
-					if (writeflag) {
-						unsigned int i;
-						debug("data={", writeflag);
-						if (len > 16) {
-							int start2 = len-16;
-							for (i=0; i<16; i++)
-								debug("%s%02x",
-								    i?",":"",
-								    data[i]);
-							debug(" .. ");
-							if (start2 < 16)
-								start2 = 16;
-							for (i=start2; i<len;
-							    i++)
-								debug("%s%02x",
-								    i?",":"",
-								    data[i]);
-						} else
-							for (i=0; i<len; i++)
-								debug("%s%02x",
-								    i?",":"",
-								    data[i]);
-						debug("}");
-					}
-#ifdef MEM_MIPS
-					symbol = get_symbol_name(
-					    &cpu->machine->symbol_context,
-					    cpu->cd.mips.pc_last, &offset);
-#else
-					symbol = "(unimpl for non-MIPS)";
-#endif
-
-/*  TODO: fix! not mips.pc_last for for example ppc  */
-
-					fatal(" paddr=%llx >= physical_max pc="
-					    "0x%08llx <%s> ]\n",
-					    (long long)paddr,
-					    (long long)cpu->cd.mips.pc_last,
-					    symbol? symbol : "no symbol");
-				}
-
-				if (cpu->machine->single_step_on_bad_addr) {
-					fatal("[ unimplemented access to "
-					    "0x%016llx, pc = 0x%016llx ]\n",
-					    (long long)paddr,
-					    (long long)cpu->pc);
-					single_step = 1;
-				}
-			}
+			if (paddr >= mem->physical_max && !no_exceptions)
+				memory_warn_about_unimplemented_addr
+				    (cpu, mem, writeflag, paddr, data, len);
 
 			if (writeflag == MEM_READ) {
-#ifdef MEM_X86
-				/*  Reading non-existant memory on x86:  */
-				memset(data, 0xff, len);
-#else
 				/*  Return all zeroes? (Or 0xff? TODO)  */
 				memset(data, 0, len);
-#endif
 
 #ifdef MEM_MIPS
 				/*
@@ -563,59 +330,69 @@
 
 	/*
 	 *  Uncached access:
+	 *
+	 *  1)  Translate the physical address to a host address.
+	 *
+	 *  2)  Insert this virtual->physical->host translation into the
+	 *      fast translation arrays (using update_translation_table()).
+	 *
+	 *  3)  If this was a Write, then invalidate any code translations
+	 *      in that page.
 	 */
-	memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag);
+	memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask,
+	    writeflag);
 	if (memblock == NULL) {
 		if (writeflag == MEM_READ)
 			memset(data, 0, len);
 		goto do_return_ok;
 	}
 
-	offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1);
+	offset = paddr & offset_mask;
 
-#ifdef BINTRANS
-	if (bintrans_cached && !bintrans_device_danger)
-		update_translation_table(cpu, vaddr & ~0xfff,
-		    memblock + (offset & ~0xfff),
-#if 0
-		    cache == CACHE_INSTRUCTION?
-			(writeflag == MEM_WRITE? 1 : 0)
-			: ok - 1,
-#else
-		    writeflag == MEM_WRITE? 1 : 0,
+	if (cpu->update_translation_table != NULL && !dyntrans_device_danger
+#ifdef MEM_MIPS
+	    /*  Ugly hack for R2000/R3000 caches:  */
+	    && (cpu->cd.mips.cpu_type.mmu_model != MMU3K ||
+            !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES))
 #endif
-		    paddr & ~0xfff);
+#ifndef MEM_MIPS
+/*	    && !(misc_flags & MEMORY_USER_ACCESS)  */
+#ifndef MEM_USERLAND
+	    && !(ok & MEMORY_NOT_FULL_PAGE)
 #endif
-
-	if (writeflag == MEM_WRITE) {
-		if (len == sizeof(uint32_t) && (offset & 3)==0)
-			*(uint32_t *)(memblock + offset) = *(uint32_t *)data;
-		else if (len == sizeof(uint8_t))
-			*(uint8_t *)(memblock + offset) = *(uint8_t *)data;
-		else
-			memcpy(memblock + offset, data, len);
-	} else {
-		if (len == sizeof(uint32_t) && (offset & 3)==0)
-			*(uint32_t *)data = *(uint32_t *)(memblock + offset);
-		else if (len == sizeof(uint8_t))
-			*(uint8_t *)data = *(uint8_t *)(memblock + offset);
-		else
-			memcpy(data, memblock + offset, len);
-
-#ifdef MEM_MIPS
-		if (cache == CACHE_INSTRUCTION) {
-			cpu->cd.mips.pc_last_host_4k_page = memblock
-			    + (offset & ~0xfff);
-#ifdef BINTRANS
-			if (bintrans_cached) {
-				cpu->cd.mips.pc_bintrans_host_4kpage =
-				    cpu->cd.mips.pc_last_host_4k_page;
-			}
 #endif
-		}
-#endif	/*  MIPS  */
-	}
+	    && !no_exceptions)
+		cpu->update_translation_table(cpu, vaddr & ~offset_mask,
+		    memblock, (misc_flags & MEMORY_USER_ACCESS) |
+#if !defined(MEM_MIPS) && !defined(MEM_USERLAND)
+		    (cache == CACHE_INSTRUCTION?
+			(writeflag == MEM_WRITE? 1 : 0) : ok - 1),
+#else
+		    (writeflag == MEM_WRITE? 1 : 0),
+#endif
+		    paddr & ~offset_mask);
 
+	/*
+	 *  If writing, or if mapping a page where writing is ok later on,
+	 *  then invalidate code translations for the (physical) page address:
+	 */
+	if ((writeflag == MEM_WRITE
+#if !defined(MEM_USERLAND)
+	    || ok == 2
+#endif
+	    ) && cpu->invalidate_code_translation != NULL)
+		cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR);
+
+	if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) {
+		printf("Write over memblock boundary?\n");
+		exit(1);
+	}
+
+	/*  And finally, read or write the data:  */
+	if (writeflag == MEM_WRITE)
+		memcpy(memblock + offset, data, len);
+	else
+		memcpy(data, memblock + offset, len);
 
 do_return_ok:
 	return MEMORY_ACCESS_OK;