--- trunk/src/memory_rw.c	2007/10/08 16:19:37	22
+++ trunk/src/memory_rw.c	2007/10/08 16:20:10	26
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: memory_rw.c,v 1.82 2005/12/31 15:48:32 debug Exp $
+ *  $Id: memory_rw.c,v 1.90 2006/06/25 00:15:44 debug Exp $
  *
  *  Generic memory_rw(), with special hacks for specific CPU families.
  *
@@ -53,10 +53,6 @@
  *  If the address indicates access to a memory mapped device, that device'
  *  read/write access function is called.
  *
- *  If instruction latency/delay support is enabled, then
- *  cpu->instruction_delay is increased by the number of instruction to
- *  delay execution.
- *
  *  This function should not be called with cpu == NULL.
  *
  *  Returns one of the following:
@@ -80,9 +76,6 @@
 	uint64_t paddr;
 	int cache, no_exceptions, offset;
 	unsigned char *memblock;
-#ifdef MEM_MIPS
-	int bintrans_cached = cpu->machine->bintrans_enable;
-#endif
 	int dyntrans_device_danger = 0;
 
 	no_exceptions = misc_flags & NO_EXCEPTIONS;
@@ -150,14 +143,6 @@
 	}
 #endif	/*  X86  */
 
-#ifdef MEM_MIPS
-	if (bintrans_cached) {
-		if (cache == CACHE_INSTRUCTION) {
-			cpu->cd.mips.pc_bintrans_host_4kpage = NULL;
-			cpu->cd.mips.pc_bintrans_paddr_valid = 0;
-		}
-	}
-#endif	/*  MEM_MIPS  */
 
 #ifdef MEM_USERLAND
 #ifdef MEM_ALPHA
@@ -165,35 +150,11 @@
 #else
 	paddr = vaddr & 0x7fffffff;
 #endif
-	goto have_paddr;
-#endif
-
-#ifndef MEM_USERLAND
-#ifdef MEM_MIPS
-	/*
-	 *  For instruction fetch, are we on the same page as the last
-	 *  instruction we fetched?
-	 *
-	 *  NOTE: There's no need to check this stuff here if this address
-	 *  is known to be in host ram, as it's done at instruction fetch
-	 *  time in cpu.c!  Only check if _host_4k_page == NULL.
-	 */
-	if (cache == CACHE_INSTRUCTION &&
-	    cpu->cd.mips.pc_last_host_4k_page == NULL &&
-	    (vaddr & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) {
-		paddr = cpu->cd.mips.pc_last_physical_page | (vaddr & 0xfff);
-		goto have_paddr;
-	}
-#endif	/*  MEM_MIPS  */
-
-	if (misc_flags & PHYSICAL || cpu->translate_address == NULL) {
+#else	/*  !MEM_USERLAND  */
+	if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) {
 		paddr = vaddr;
-#ifdef MEM_ALPHA
-		/*  paddr &= 0x1fffffff;  For testalpha  */
-		paddr &= 0x000003ffffffffffULL;
-#endif
 	} else {
-		ok = cpu->translate_address(cpu, vaddr, &paddr,
+		ok = cpu->translate_v2p(cpu, vaddr, &paddr,
 		    (writeflag? FLAG_WRITEFLAG : 0) +
 		    (no_exceptions? FLAG_NOEXCEPTIONS : 0)
 #ifdef MEM_X86
@@ -226,43 +187,7 @@
 #endif
 	}
 #endif
-
-#ifdef MEM_MIPS
-	/*
-	 *  If correct cache emulation is enabled, and we need to simluate
-	 *  cache misses even from the instruction cache, we can't run directly
-	 *  from a host page. :-/
-	 */
-#if defined(ENABLE_CACHE_EMULATION) && defined(ENABLE_INSTRUCTION_DELAYS)
-#else
-	if (cache == CACHE_INSTRUCTION) {
-		cpu->cd.mips.pc_last_virtual_page = vaddr & ~0xfff;
-		cpu->cd.mips.pc_last_physical_page = paddr & ~0xfff;
-		cpu->cd.mips.pc_last_host_4k_page = NULL;
-
-		/*  _last_host_4k_page will be set to 1 further down,
-		    if the page is actually in host ram  */
-	}
-#endif
-#endif	/*  MEM_MIPS  */
-#endif	/*  ifndef MEM_USERLAND  */
-
-
-#if defined(MEM_MIPS) || defined(MEM_USERLAND)
-have_paddr:
-#endif
-
-
-#ifdef MEM_MIPS
-	/*  TODO: How about bintrans vs cache emulation?  */
-	if (bintrans_cached) {
-		if (cache == CACHE_INSTRUCTION) {
-			cpu->cd.mips.pc_bintrans_paddr_valid = 1;
-			cpu->cd.mips.pc_bintrans_paddr = paddr;
-		}
-	}
-#endif	/*  MEM_MIPS  */
-
+#endif	/*  !MEM_USERLAND  */
 
 
 #ifndef MEM_USERLAND
@@ -376,17 +301,9 @@
 					    data, len, writeflag,
 					    mem->dev_extra[i]);
 
-#ifdef ENABLE_INSTRUCTION_DELAYS
 				if (res == 0)
 					res = -1;
 
-#ifdef MEM_MIPS
-				cpu->cd.mips.instruction_delay +=
-				    ( (abs(res) - 1) *
-				     cpu->cd.mips.cpu_type.instrs_per_cycle );
-#endif
-#endif
-
 #ifndef MEM_X86
 				/*
 				 *  If accessing the memory mapped device
@@ -455,13 +372,8 @@
 #endif /* MIPS */
 		{
 			if (paddr >= mem->physical_max) {
+				uint64_t offset, old_pc = cpu->pc;
 				char *symbol;
-				uint64_t offset;
-#ifdef MEM_MIPS
-				uint64_t old_pc = cpu->cd.mips.pc_last;
-#else
-				uint64_t old_pc = cpu->pc;
-#endif
 
 				/*  This allows for example OS kernels to probe
 				    memory a few KBs past the end of memory,
@@ -508,18 +420,6 @@
 					fatal(" <%s> ]\n",
 					    symbol? symbol : " no symbol ");
 				}
-
-				if (cpu->machine->single_step_on_bad_addr) {
-					fatal("[ unimplemented access to "
-					    "0x%llx, pc=0x",(long long)paddr);
-					if (cpu->is_32bit)
-						fatal("%08x ]\n",
-						    (int)old_pc);
-					else
-						fatal("%016llx ]\n",
-						    (long long)old_pc);
-					single_step = 1;
-				}
 			}
 
 			if (writeflag == MEM_READ) {
@@ -579,6 +479,11 @@
 	offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1);
 
 	if (cpu->update_translation_table != NULL && !dyntrans_device_danger
+#ifdef MEM_MIPS
+	    /*  Ugly hack for R2000/R3000 caches:  */
+	    && (cpu->cd.mips.cpu_type.mmu_model != MMU3K ||
+            !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES))
+#endif
 #ifndef MEM_MIPS
 /*	    && !(misc_flags & MEMORY_USER_ACCESS)  */
 #ifndef MEM_USERLAND
@@ -589,9 +494,6 @@
 		cpu->update_translation_table(cpu, vaddr & ~offset_mask,
 		    memblock + (offset & ~offset_mask),
 		    (misc_flags & MEMORY_USER_ACCESS) |
-#ifndef MEM_MIPS
-		    (cache == CACHE_INSTRUCTION? TLB_CODE : 0) |
-#endif
 #if !defined(MEM_MIPS) && !defined(MEM_USERLAND)
 		    (cache == CACHE_INSTRUCTION?
 			(writeflag == MEM_WRITE? 1 : 0) : ok - 1),
@@ -622,17 +524,6 @@
 			*(uint8_t *)data = *(uint8_t *)(memblock + offset);
 		else
 			memcpy(data, memblock + offset, len);
-
-#ifdef MEM_MIPS
-		if (cache == CACHE_INSTRUCTION) {
-			cpu->cd.mips.pc_last_host_4k_page = memblock
-			    + (offset & ~offset_mask);
-			if (bintrans_cached) {
-				cpu->cd.mips.pc_bintrans_host_4kpage =
-				    cpu->cd.mips.pc_last_host_4k_page;
-			}
-		}
-#endif	/*  MIPS  */
 	}