--- trunk/src/memory_rw.c 2007/10/08 16:19:11 18 +++ trunk/src/memory_rw.c 2007/10/08 16:19:23 20 @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * - * $Id: memory_rw.c,v 1.75 2005/10/27 14:01:12 debug Exp $ + * $Id: memory_rw.c,v 1.80 2005/11/20 11:28:44 debug Exp $ * * Generic memory_rw(), with special hacks for specific CPU families. * @@ -48,7 +48,7 @@ * a placeholder for data when reading from memory * len the length of the 'data' buffer * writeflag set to MEM_READ or MEM_WRITE - * cache_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags + * misc_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags * * If the address indicates access to a memory mapped device, that device' * read/write access function is called. @@ -66,7 +66,7 @@ * (MEMORY_ACCESS_FAILED is 0.) */ int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, - unsigned char *data, size_t len, int writeflag, int cache_flags) + unsigned char *data, size_t len, int writeflag, int misc_flags) { #ifdef MEM_ALPHA const int offset_mask = 0x1fff; @@ -85,24 +85,24 @@ #endif int bintrans_device_danger = 0; - no_exceptions = cache_flags & NO_EXCEPTIONS; - cache = cache_flags & CACHE_FLAGS_MASK; + no_exceptions = misc_flags & NO_EXCEPTIONS; + cache = misc_flags & CACHE_FLAGS_MASK; #ifdef MEM_X86 /* Real-mode wrap-around: */ - if (REAL_MODE && !(cache_flags & PHYSICAL)) { + if (REAL_MODE && !(misc_flags & PHYSICAL)) { if ((vaddr & 0xffff) + len > 0x10000) { /* Do one byte at a time: */ int res = 0, i; for (i=0; i 0x1000 && !(cache_flags & PHYSICAL) + if ((vaddr & 0xfff) + len > 0x1000 && !(misc_flags & PHYSICAL) && cpu->cd.x86.cr[0] & X86_CR0_PG) { /* For WRITES: Read ALL BYTES FIRST and write them back!!! Then do a write of all the new bytes. This is to make sure @@ -113,17 +113,17 @@ unsigned char tmp; for (i=0; itranslate_address == NULL) { + if (misc_flags & PHYSICAL || cpu->translate_address == NULL) { paddr = vaddr; - #ifdef MEM_ALPHA /* paddr &= 0x1fffffff; For testalpha */ paddr &= 0x000003ffffffffffULL; #endif - -#ifdef MEM_IA64 - /* For testia64 */ - paddr &= 0x3fffffff; -#endif - -#ifdef MEM_PPC - if (cpu->cd.ppc.bits == 32) - paddr &= 0xffffffff; -#endif - -#ifdef MEM_SH - paddr &= 0xffffffff; -#endif } else { ok = cpu->translate_address(cpu, vaddr, &paddr, (writeflag? FLAG_WRITEFLAG : 0) + (no_exceptions? FLAG_NOEXCEPTIONS : 0) #ifdef MEM_X86 - + (cache_flags & NO_SEGMENTATION) + + (misc_flags & NO_SEGMENTATION) #endif #ifdef MEM_ARM - + (cache_flags & MEMORY_USER_ACCESS) + + (misc_flags & MEMORY_USER_ACCESS) #endif + (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); /* If the translation caused an exception, or was invalid in @@ -226,7 +211,7 @@ #ifdef MEM_X86 /* DOS debugging :-) */ - if (!quiet_mode && !(cache_flags & PHYSICAL)) { + if (!quiet_mode && !(misc_flags & PHYSICAL)) { if (paddr >= 0x400 && paddr <= 0x4ff) debug("{ PC BIOS DATA AREA: %s 0x%x }\n", writeflag == MEM_WRITE? "writing to" : "reading from", @@ -329,12 +314,13 @@ len = mem->dev_length[i] - paddr; if (cpu->update_translation_table != NULL && - mem->dev_flags[i] & MEM_DYNTRANS_OK) { + !(ok & MEMORY_NOT_FULL_PAGE) && + mem->dev_flags[i] & DM_DYNTRANS_OK) { int wf = writeflag == MEM_WRITE? 1 : 0; unsigned char *host_addr; if (!(mem->dev_flags[i] & - MEM_DYNTRANS_WRITE_OK)) + DM_DYNTRANS_WRITE_OK)) wf = 0; if (writeflag && wf) { @@ -353,7 +339,7 @@ } if (mem->dev_flags[i] & - MEM_EMULATED_RAM) { + DM_EMULATED_RAM) { /* MEM_WRITE to force the page to be allocated, if it wasn't already */ @@ -378,7 +364,7 @@ res = 0; if (!no_exceptions || (mem->dev_flags[i] & - MEM_READING_HAS_NO_SIDE_EFFECTS)) + DM_READS_HAVE_NO_SIDE_EFFECTS)) res = mem->dev_f[i](cpu, mem, paddr, data, len, writeflag, mem->dev_extra[i]); @@ -429,7 +415,7 @@ switch (cpu->cd.mips.cpu_type.mmu_model) { case MMU3K: /* if not uncached addess (TODO: generalize this) */ - if (!(cache_flags & PHYSICAL) && cache != CACHE_NONE && + if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE && !((vaddr & 0xffffffffULL) >= 0xa0000000ULL && (vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { if (memory_cache_R3000(cpu, cache, paddr, @@ -461,15 +447,11 @@ { if (paddr >= mem->physical_max) { char *symbol; - uint64_t old_pc; uint64_t offset; - #ifdef MEM_MIPS - old_pc = cpu->cd.mips.pc_last; + uint64_t old_pc = cpu->cd.mips.pc_last; #else - /* Default instruction size on most - RISC archs is 32 bits: */ - old_pc = cpu->pc - sizeof(uint32_t); + uint64_t old_pc = cpu->pc; #endif /* This allows for example OS kernels to probe @@ -589,7 +571,7 @@ if (cpu->update_translation_table != NULL && !bintrans_device_danger #ifndef MEM_MIPS -/* && !(cache_flags & MEMORY_USER_ACCESS) */ +/* && !(misc_flags & MEMORY_USER_ACCESS) */ #ifndef MEM_USERLAND && !(ok & MEMORY_NOT_FULL_PAGE) #endif @@ -597,22 +579,20 @@ && !no_exceptions) cpu->update_translation_table(cpu, vaddr & ~offset_mask, memblock + (offset & ~offset_mask), - (cache_flags & MEMORY_USER_ACCESS) | + (misc_flags & MEMORY_USER_ACCESS) | #ifndef MEM_MIPS (cache == CACHE_INSTRUCTION? TLB_CODE : 0) | #endif -#if 0 +#if !defined(MEM_MIPS) && !defined(MEM_USERLAND) (cache == CACHE_INSTRUCTION? - (writeflag == MEM_WRITE? 1 : 0) - : ok - 1), + (writeflag == MEM_WRITE? 1 : 0) : ok - 1), #else (writeflag == MEM_WRITE? 1 : 0), #endif paddr & ~offset_mask); /* Invalidate code translations for the page we are writing to. */ - if (writeflag == MEM_WRITE && - cpu->invalidate_code_translation != NULL) + if (writeflag == MEM_WRITE && cpu->invalidate_code_translation != NULL) cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR); if (writeflag == MEM_WRITE) {