25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_rw.c,v 1.87 2006/06/22 11:43:03 debug Exp $ |
* $Id: memory_rw.c,v 1.90 2006/06/25 00:15:44 debug Exp $ |
29 |
* |
* |
30 |
* Generic memory_rw(), with special hacks for specific CPU families. |
* Generic memory_rw(), with special hacks for specific CPU families. |
31 |
* |
* |
151 |
paddr = vaddr & 0x7fffffff; |
paddr = vaddr & 0x7fffffff; |
152 |
#endif |
#endif |
153 |
#else /* !MEM_USERLAND */ |
#else /* !MEM_USERLAND */ |
154 |
if (misc_flags & PHYSICAL || cpu->translate_address == NULL) { |
if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) { |
155 |
paddr = vaddr; |
paddr = vaddr; |
156 |
} else { |
} else { |
157 |
ok = cpu->translate_address(cpu, vaddr, &paddr, |
ok = cpu->translate_v2p(cpu, vaddr, &paddr, |
158 |
(writeflag? FLAG_WRITEFLAG : 0) + |
(writeflag? FLAG_WRITEFLAG : 0) + |
159 |
(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
160 |
#ifdef MEM_X86 |
#ifdef MEM_X86 |
479 |
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); |
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); |
480 |
|
|
481 |
if (cpu->update_translation_table != NULL && !dyntrans_device_danger |
if (cpu->update_translation_table != NULL && !dyntrans_device_danger |
482 |
|
#ifdef MEM_MIPS |
483 |
|
/* Ugly hack for R2000/R3000 caches: */ |
484 |
|
&& (cpu->cd.mips.cpu_type.mmu_model != MMU3K || |
485 |
|
!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)) |
486 |
|
#endif |
487 |
#ifndef MEM_MIPS |
#ifndef MEM_MIPS |
488 |
/* && !(misc_flags & MEMORY_USER_ACCESS) */ |
/* && !(misc_flags & MEMORY_USER_ACCESS) */ |
489 |
#ifndef MEM_USERLAND |
#ifndef MEM_USERLAND |
494 |
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
495 |
memblock + (offset & ~offset_mask), |
memblock + (offset & ~offset_mask), |
496 |
(misc_flags & MEMORY_USER_ACCESS) | |
(misc_flags & MEMORY_USER_ACCESS) | |
|
#ifndef MEM_MIPS |
|
|
(cache == CACHE_INSTRUCTION? TLB_CODE : 0) | |
|
|
#endif |
|
497 |
#if !defined(MEM_MIPS) && !defined(MEM_USERLAND) |
#if !defined(MEM_MIPS) && !defined(MEM_USERLAND) |
498 |
(cache == CACHE_INSTRUCTION? |
(cache == CACHE_INSTRUCTION? |
499 |
(writeflag == MEM_WRITE? 1 : 0) : ok - 1), |
(writeflag == MEM_WRITE? 1 : 0) : ok - 1), |