/[gxemul]/trunk/src/machines/machine_test.c
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Contents of /trunk/src/machines/machine_test.c

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 12131 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: machine_test.c,v 1.17 2006/07/20 21:53:00 debug Exp $
29 *
30 * Various "test" machines (bare machines with just a CPU, or a bare machine
31 * plus some experimental devices).
32 */
33
34 #include <stdio.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "device.h"
39 #include "devices.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43
44 #include "testmachine/dev_cons.h"
45 #include "testmachine/dev_disk.h"
46 #include "testmachine/dev_ether.h"
47 #include "testmachine/dev_fb.h"
48 #include "testmachine/dev_mp.h"
49
50
51 static void default_test(struct machine *machine, struct cpu *cpu)
52 {
53 char tmpstr[1000];
54
55 snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=0",
56 (uint64_t) DEV_CONS_ADDRESS);
57 machine->main_console_handle = (size_t)device_add(machine, tmpstr);
58
59 snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
60 (uint64_t) DEV_MP_ADDRESS);
61 device_add(machine, tmpstr);
62
63 snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
64 (uint64_t) DEV_FBCTRL_ADDRESS);
65 device_add(machine, tmpstr);
66
67 snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
68 (uint64_t) DEV_DISK_ADDRESS);
69 device_add(machine, tmpstr);
70
71 snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=0",
72 (uint64_t) DEV_ETHER_ADDRESS);
73 device_add(machine, tmpstr);
74 }
75
76
77 MACHINE_SETUP(barealpha)
78 {
79 machine->machine_name = "Generic \"bare\" Alpha machine";
80 machine->stable = 1;
81 }
82
83
84 MACHINE_SETUP(testalpha)
85 {
86 machine->machine_name = "Alpha test machine";
87 machine->stable = 1;
88
89 /* TODO: interrupt for Alpha? */
90
91 default_test(machine, cpu);
92 }
93
94
95 MACHINE_DEFAULT_CPU(barealpha)
96 {
97 machine->cpu_name = strdup("21264");
98 }
99
100
101 MACHINE_DEFAULT_CPU(testalpha)
102 {
103 machine->cpu_name = strdup("21264");
104 }
105
106
107 MACHINE_REGISTER(barealpha)
108 {
109 MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
110 ARCH_ALPHA, MACHINE_BAREALPHA);
111
112 machine_entry_add_alias(me, "barealpha");
113 }
114
115
116 MACHINE_REGISTER(testalpha)
117 {
118 MR_DEFAULT(testalpha, "Test-machine for Alpha",
119 ARCH_ALPHA, MACHINE_TESTALPHA);
120
121 machine_entry_add_alias(me, "testalpha");
122 }
123
124
125 MACHINE_SETUP(barearm)
126 {
127 machine->machine_name = "Generic \"bare\" ARM machine";
128 machine->stable = 1;
129 }
130
131
132 MACHINE_SETUP(testarm)
133 {
134 machine->machine_name = "ARM test machine";
135 machine->stable = 1;
136
137 /* TODO: interrupt for ARM? */
138
139 default_test(machine, cpu);
140
141 /*
142 * Place a tiny stub at end of memory, and set the link register to
143 * point to it. This stub halts the machine (making it easy to try
144 * out simple stand-alone C functions).
145 */
146 cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
147 cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
148 store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
149 store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
150 store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
151 }
152
153
154 MACHINE_DEFAULT_CPU(barearm)
155 {
156 machine->cpu_name = strdup("SA1110");
157 }
158
159
160 MACHINE_DEFAULT_CPU(testarm)
161 {
162 machine->cpu_name = strdup("SA1110");
163 }
164
165
166 MACHINE_REGISTER(barearm)
167 {
168 MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
169 ARCH_ARM, MACHINE_BAREARM);
170
171 machine_entry_add_alias(me, "barearm");
172 }
173
174
175 MACHINE_REGISTER(testarm)
176 {
177 MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);
178
179 machine_entry_add_alias(me, "testarm");
180 }
181
182
183
184 MACHINE_SETUP(barehppa)
185 {
186 machine->machine_name = "Generic \"bare\" HPPA machine";
187 machine->stable = 1;
188 }
189
190
191 MACHINE_SETUP(testhppa)
192 {
193 machine->machine_name = "HPPA test machine";
194 machine->stable = 1;
195
196 /* TODO: interrupt for HPPA? */
197
198 default_test(machine, cpu);
199 }
200
201
202 MACHINE_DEFAULT_CPU(barehppa)
203 {
204 machine->cpu_name = strdup("HPPA");
205 }
206
207
208 MACHINE_DEFAULT_CPU(testhppa)
209 {
210 machine->cpu_name = strdup("HPPA");
211 }
212
213
214 MACHINE_REGISTER(barehppa)
215 {
216 MR_DEFAULT(barehppa, "Generic \"bare\" HPPA machine",
217 ARCH_HPPA, MACHINE_BAREHPPA);
218
219 machine_entry_add_alias(me, "barehppa");
220 }
221
222
223 MACHINE_REGISTER(testhppa)
224 {
225 MR_DEFAULT(testhppa, "Test-machine for HPPA",
226 ARCH_HPPA, MACHINE_TESTHPPA);
227
228 machine_entry_add_alias(me, "testhppa");
229 }
230
231
232 MACHINE_SETUP(barei960)
233 {
234 machine->machine_name = "Generic \"bare\" i960 machine";
235 machine->stable = 1;
236 }
237
238
239 MACHINE_SETUP(testi960)
240 {
241 machine->machine_name = "i960 test machine";
242 machine->stable = 1;
243
244 /* TODO: interrupt for i960? */
245
246 default_test(machine, cpu);
247 }
248
249
250 MACHINE_DEFAULT_CPU(barei960)
251 {
252 machine->cpu_name = strdup("i960");
253 }
254
255
256 MACHINE_DEFAULT_CPU(testi960)
257 {
258 machine->cpu_name = strdup("i960");
259 }
260
261
262 MACHINE_REGISTER(barei960)
263 {
264 MR_DEFAULT(barei960, "Generic \"bare\" i960 machine",
265 ARCH_I960, MACHINE_BAREI960);
266
267 machine_entry_add_alias(me, "barei960");
268 }
269
270
271 MACHINE_REGISTER(testi960)
272 {
273 MR_DEFAULT(testi960, "Test-machine for i960",
274 ARCH_I960, MACHINE_TESTI960);
275
276 machine_entry_add_alias(me, "testi960");
277 }
278
279
280 MACHINE_SETUP(bareia64)
281 {
282 machine->machine_name = "Generic \"bare\" IA64 machine";
283 machine->stable = 1;
284 }
285
286
287 MACHINE_SETUP(testia64)
288 {
289 machine->machine_name = "IA64 test machine";
290 machine->stable = 1;
291
292 /* TODO: interrupt for IA64? */
293
294 default_test(machine, cpu);
295 }
296
297
298 MACHINE_DEFAULT_CPU(bareia64)
299 {
300 machine->cpu_name = strdup("IA64");
301 }
302
303
304 MACHINE_DEFAULT_CPU(testia64)
305 {
306 machine->cpu_name = strdup("IA64");
307 }
308
309
310 MACHINE_REGISTER(bareia64)
311 {
312 MR_DEFAULT(bareia64, "Generic \"bare\" IA64 machine",
313 ARCH_IA64, MACHINE_BAREIA64);
314
315 machine_entry_add_alias(me, "bareia64");
316 }
317
318
319 MACHINE_REGISTER(testia64)
320 {
321 MR_DEFAULT(testia64, "Test-machine for IA64",
322 ARCH_IA64, MACHINE_TESTIA64);
323
324 machine_entry_add_alias(me, "testia64");
325 }
326
327
328 MACHINE_SETUP(barem68k)
329 {
330 machine->machine_name = "Generic \"bare\" M68K machine";
331 machine->stable = 1;
332 }
333
334
335 MACHINE_SETUP(testm68k)
336 {
337 machine->machine_name = "M68K test machine";
338 machine->stable = 1;
339
340 /* TODO: interrupt for M68K? */
341
342 default_test(machine, cpu);
343 }
344
345
346 MACHINE_DEFAULT_CPU(barem68k)
347 {
348 machine->cpu_name = strdup("68020");
349 }
350
351
352 MACHINE_DEFAULT_CPU(testm68k)
353 {
354 machine->cpu_name = strdup("68020");
355 }
356
357
358 MACHINE_REGISTER(barem68k)
359 {
360 MR_DEFAULT(barem68k, "Generic \"bare\" M68K machine",
361 ARCH_M68K, MACHINE_BAREM68K);
362
363 machine_entry_add_alias(me, "barem68k");
364 }
365
366
367 MACHINE_REGISTER(testm68k)
368 {
369 MR_DEFAULT(testm68k, "Test-machine for M68K",
370 ARCH_M68K, MACHINE_TESTM68K);
371
372 machine_entry_add_alias(me, "testm68k");
373 }
374
375
376 MACHINE_SETUP(baremips)
377 {
378 machine->machine_name = "Generic \"bare\" MIPS machine";
379 machine->stable = 1;
380 cpu->byte_order = EMUL_BIG_ENDIAN;
381 }
382
383
384 MACHINE_SETUP(testmips)
385 {
386 /*
387 * A MIPS test machine (which happens to work with the
388 * code in my master's thesis). :-)
389 *
390 * IRQ map:
391 * 7 CPU counter
392 * 6 SMP IPIs
393 * 5 not used yet
394 * 4 not used yet
395 * 3 ethernet
396 * 2 serial console
397 */
398
399 char tmpstr[1000];
400
401 machine->machine_name = "MIPS test machine";
402 machine->stable = 1;
403 cpu->byte_order = EMUL_BIG_ENDIAN;
404
405 snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=2",
406 (uint64_t) DEV_CONS_ADDRESS);
407 machine->main_console_handle = (size_t)device_add(machine, tmpstr);
408
409 snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
410 (uint64_t) DEV_MP_ADDRESS);
411 device_add(machine, tmpstr);
412
413 snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
414 (uint64_t) DEV_FBCTRL_ADDRESS);
415 device_add(machine, tmpstr);
416
417 snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
418 (uint64_t) DEV_DISK_ADDRESS);
419 device_add(machine, tmpstr);
420
421 snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=3",
422 (uint64_t) DEV_ETHER_ADDRESS);
423 device_add(machine, tmpstr);
424 }
425
426
427 MACHINE_DEFAULT_CPU(baremips)
428 {
429 machine->cpu_name = strdup("5Kc");
430 }
431
432
433 MACHINE_DEFAULT_CPU(testmips)
434 {
435 machine->cpu_name = strdup("5Kc");
436 }
437
438
439 MACHINE_REGISTER(baremips)
440 {
441 MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
442 ARCH_MIPS, MACHINE_BAREMIPS);
443
444 machine_entry_add_alias(me, "baremips");
445 }
446
447
448 MACHINE_REGISTER(testmips)
449 {
450 MR_DEFAULT(testmips, "Test-machine for MIPS",
451 ARCH_MIPS, MACHINE_TESTMIPS);
452
453 machine_entry_add_alias(me, "testmips");
454 }
455
456
457 MACHINE_SETUP(bareppc)
458 {
459 machine->machine_name = "Generic \"bare\" PPC machine";
460 machine->stable = 1;
461 }
462
463
464 MACHINE_SETUP(testppc)
465 {
466 machine->machine_name = "PPC test machine";
467 machine->stable = 1;
468
469 /* TODO: interrupt for PPC? */
470
471 default_test(machine, cpu);
472 }
473
474
475 MACHINE_DEFAULT_CPU(bareppc)
476 {
477 machine->cpu_name = strdup("PPC970");
478 }
479
480
481 MACHINE_DEFAULT_CPU(testppc)
482 {
483 machine->cpu_name = strdup("PPC970");
484 }
485
486
487 MACHINE_REGISTER(bareppc)
488 {
489 MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
490 ARCH_PPC, MACHINE_BAREPPC);
491
492 machine_entry_add_alias(me, "bareppc");
493 }
494
495
496 MACHINE_REGISTER(testppc)
497 {
498 MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);
499
500 machine_entry_add_alias(me, "testppc");
501 }
502
503
504 MACHINE_SETUP(baresh)
505 {
506 machine->machine_name = "Generic \"bare\" SH machine";
507 machine->stable = 1;
508 }
509
510
511 MACHINE_SETUP(testsh)
512 {
513 machine->machine_name = "SH test machine";
514 machine->stable = 1;
515
516 /* TODO: interrupt for SH? */
517
518 default_test(machine, cpu);
519 }
520
521
522 MACHINE_DEFAULT_CPU(baresh)
523 {
524 machine->cpu_name = strdup("SH");
525 }
526
527
528 MACHINE_DEFAULT_CPU(testsh)
529 {
530 machine->cpu_name = strdup("SH");
531 }
532
533
534 MACHINE_REGISTER(baresh)
535 {
536 MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
537 ARCH_SH, MACHINE_BARESH);
538
539 machine_entry_add_alias(me, "baresh");
540 }
541
542
543 MACHINE_REGISTER(testsh)
544 {
545 MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);
546
547 machine_entry_add_alias(me, "testsh");
548 }
549
550
551 MACHINE_SETUP(baresparc)
552 {
553 machine->machine_name = "Generic \"bare\" SPARC machine";
554 machine->stable = 1;
555 }
556
557
558 MACHINE_SETUP(testsparc)
559 {
560 machine->machine_name = "SPARC test machine";
561 machine->stable = 1;
562
563 /* TODO: interrupt for SPARC? */
564
565 default_test(machine, cpu);
566 }
567
568
569 MACHINE_DEFAULT_CPU(baresparc)
570 {
571 machine->cpu_name = strdup("UltraSPARC");
572 }
573
574
575 MACHINE_DEFAULT_CPU(testsparc)
576 {
577 machine->cpu_name = strdup("UltraSPARC");
578 }
579
580
581 MACHINE_REGISTER(baresparc)
582 {
583 MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
584 ARCH_SPARC, MACHINE_BARESPARC);
585
586 machine_entry_add_alias(me, "baresparc");
587 }
588
589
590 MACHINE_REGISTER(testsparc)
591 {
592 MR_DEFAULT(testsparc, "Test-machine for SPARC",
593 ARCH_SPARC, MACHINE_TESTSPARC);
594
595 machine_entry_add_alias(me, "testsparc");
596 }
597
598
599 MACHINE_SETUP(baretransputer)
600 {
601 machine->machine_name = "Generic \"bare\" Transputer machine";
602 machine->stable = 1;
603 }
604
605
606 MACHINE_DEFAULT_CPU(baretransputer)
607 {
608 machine->cpu_name = strdup("T800");
609 }
610
611
612 MACHINE_REGISTER(baretransputer)
613 {
614 MR_DEFAULT(baretransputer, "Generic \"bare\" Transputer machine",
615 ARCH_TRANSPUTER, MACHINE_BARETRANSPUTER);
616
617 machine_entry_add_alias(me, "baretransputer");
618 }
619

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