/[gxemul]/trunk/src/machines/machine_test.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/machines/machine_test.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 10513 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: machine_test.c,v 1.30 2007/02/10 14:38:39 debug Exp $
29 *
30 * Various "test" machines (bare machines with just a CPU, or a bare machine
31 * plus some experimental devices).
32 */
33
34 #include <stdio.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "device.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42
43 #include "testmachine/dev_cons.h"
44 #include "testmachine/dev_disk.h"
45 #include "testmachine/dev_ether.h"
46 #include "testmachine/dev_fb.h"
47 #include "testmachine/dev_mp.h"
48 #include "testmachine/dev_rtc.h"
49
50
51 static void default_test(struct machine *machine, struct cpu *cpu)
52 {
53 char tmpstr[1000];
54
55 snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=none",
56 (uint64_t) DEV_CONS_ADDRESS);
57 machine->main_console_handle = (size_t)device_add(machine, tmpstr);
58
59 snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
60 (uint64_t) DEV_MP_ADDRESS);
61 device_add(machine, tmpstr);
62
63 snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
64 (uint64_t) DEV_FBCTRL_ADDRESS);
65 device_add(machine, tmpstr);
66
67 snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
68 (uint64_t) DEV_DISK_ADDRESS);
69 device_add(machine, tmpstr);
70
71 snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=none",
72 (uint64_t) DEV_ETHER_ADDRESS);
73 device_add(machine, tmpstr);
74
75 snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=none",
76 (uint64_t) DEV_RTC_ADDRESS);
77 device_add(machine, tmpstr);
78 }
79
80
81 MACHINE_SETUP(barealpha)
82 {
83 machine->machine_name = "Generic \"bare\" Alpha machine";
84 machine->stable = 1;
85 }
86
87
88 MACHINE_SETUP(testalpha)
89 {
90 machine->machine_name = "Alpha test machine";
91 machine->stable = 1;
92
93 /* TODO: interrupt for Alpha? */
94
95 default_test(machine, cpu);
96 }
97
98
99 MACHINE_DEFAULT_CPU(barealpha)
100 {
101 machine->cpu_name = strdup("21264");
102 }
103
104
105 MACHINE_DEFAULT_CPU(testalpha)
106 {
107 machine->cpu_name = strdup("21264");
108 }
109
110
111 MACHINE_REGISTER(barealpha)
112 {
113 MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
114 ARCH_ALPHA, MACHINE_BAREALPHA);
115
116 machine_entry_add_alias(me, "barealpha");
117 }
118
119
120 MACHINE_REGISTER(testalpha)
121 {
122 MR_DEFAULT(testalpha, "Test-machine for Alpha",
123 ARCH_ALPHA, MACHINE_TESTALPHA);
124
125 machine_entry_add_alias(me, "testalpha");
126 }
127
128
129 MACHINE_SETUP(barearm)
130 {
131 machine->machine_name = "Generic \"bare\" ARM machine";
132 machine->stable = 1;
133 }
134
135
136 MACHINE_SETUP(testarm)
137 {
138 machine->machine_name = "ARM test machine";
139 machine->stable = 1;
140
141 /* TODO: interrupt for ARM? */
142
143 default_test(machine, cpu);
144
145 /*
146 * Place a tiny stub at end of memory, and set the link register to
147 * point to it. This stub halts the machine (making it easy to try
148 * out simple stand-alone C functions).
149 */
150 cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
151 cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
152 store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
153 store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
154 store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
155 }
156
157
158 MACHINE_DEFAULT_CPU(barearm)
159 {
160 machine->cpu_name = strdup("SA1110");
161 }
162
163
164 MACHINE_DEFAULT_CPU(testarm)
165 {
166 machine->cpu_name = strdup("SA1110");
167 }
168
169
170 MACHINE_REGISTER(barearm)
171 {
172 MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
173 ARCH_ARM, MACHINE_BAREARM);
174
175 machine_entry_add_alias(me, "barearm");
176 }
177
178
179 MACHINE_REGISTER(testarm)
180 {
181 MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);
182
183 machine_entry_add_alias(me, "testarm");
184 }
185
186
187
188 MACHINE_SETUP(barem68k)
189 {
190 machine->machine_name = "Generic \"bare\" M68K machine";
191 machine->stable = 1;
192 }
193
194
195 MACHINE_SETUP(testm68k)
196 {
197 machine->machine_name = "M68K test machine";
198 machine->stable = 1;
199
200 /* TODO: interrupt for M68K? */
201
202 default_test(machine, cpu);
203 }
204
205
206 MACHINE_DEFAULT_CPU(barem68k)
207 {
208 machine->cpu_name = strdup("68020");
209 }
210
211
212 MACHINE_DEFAULT_CPU(testm68k)
213 {
214 machine->cpu_name = strdup("68020");
215 }
216
217
218 MACHINE_REGISTER(barem68k)
219 {
220 MR_DEFAULT(barem68k, "Generic \"bare\" M68K machine",
221 ARCH_M68K, MACHINE_BAREM68K);
222
223 machine_entry_add_alias(me, "barem68k");
224 }
225
226
227 MACHINE_REGISTER(testm68k)
228 {
229 MR_DEFAULT(testm68k, "Test-machine for M68K",
230 ARCH_M68K, MACHINE_TESTM68K);
231
232 machine_entry_add_alias(me, "testm68k");
233 }
234
235
236 MACHINE_SETUP(baremips)
237 {
238 machine->machine_name = "Generic \"bare\" MIPS machine";
239 machine->stable = 1;
240 cpu->byte_order = EMUL_BIG_ENDIAN;
241 }
242
243
244 MACHINE_SETUP(testmips)
245 {
246 /*
247 * A MIPS test machine. Originally, this was created as a way for
248 * me to test my master's thesis code; since then it has both
249 * evolved to support new things, and suffered bit rot so that it
250 * no longer can run my thesis code. Well, well...
251 *
252 * IRQ map:
253 * 7 CPU counter
254 * 6 SMP IPIs
255 * 5 not used yet
256 * 4 rtc
257 * 3 ethernet
258 * 2 serial console
259 */
260
261 char tmpstr[300];
262
263 machine->machine_name = "MIPS test machine";
264 machine->stable = 1;
265 cpu->byte_order = EMUL_BIG_ENDIAN;
266
267 snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=%s."
268 "cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
269 machine->bootstrap_cpu);
270 machine->main_console_handle = (size_t)device_add(machine, tmpstr);
271
272 snprintf(tmpstr, sizeof(tmpstr), "mp irq=6 addr=0x%"PRIx64,
273 (uint64_t) DEV_MP_ADDRESS);
274 device_add(machine, tmpstr);
275
276 snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
277 (uint64_t) DEV_FBCTRL_ADDRESS);
278 device_add(machine, tmpstr);
279
280 snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
281 (uint64_t) DEV_DISK_ADDRESS);
282 device_add(machine, tmpstr);
283
284 snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s."
285 "cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
286 machine->bootstrap_cpu);
287 device_add(machine, tmpstr);
288
289 snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s."
290 "cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
291 machine->bootstrap_cpu);
292 device_add(machine, tmpstr);
293 }
294
295
296 MACHINE_DEFAULT_CPU(baremips)
297 {
298 machine->cpu_name = strdup("5KE");
299 }
300
301
302 MACHINE_DEFAULT_CPU(testmips)
303 {
304 machine->cpu_name = strdup("5KE");
305 }
306
307
308 MACHINE_REGISTER(baremips)
309 {
310 MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
311 ARCH_MIPS, MACHINE_BAREMIPS);
312
313 machine_entry_add_alias(me, "baremips");
314 }
315
316
317 MACHINE_REGISTER(testmips)
318 {
319 MR_DEFAULT(testmips, "Test-machine for MIPS",
320 ARCH_MIPS, MACHINE_TESTMIPS);
321
322 machine_entry_add_alias(me, "testmips");
323 }
324
325
326 MACHINE_SETUP(bareppc)
327 {
328 machine->machine_name = "Generic \"bare\" PPC machine";
329 machine->stable = 1;
330 }
331
332
333 MACHINE_SETUP(testppc)
334 {
335 machine->machine_name = "PPC test machine";
336 machine->stable = 1;
337
338 /* TODO: interrupt for PPC? */
339
340 default_test(machine, cpu);
341 }
342
343
344 MACHINE_DEFAULT_CPU(bareppc)
345 {
346 machine->cpu_name = strdup("PPC970");
347 }
348
349
350 MACHINE_DEFAULT_CPU(testppc)
351 {
352 machine->cpu_name = strdup("PPC970");
353 }
354
355
356 MACHINE_REGISTER(bareppc)
357 {
358 MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
359 ARCH_PPC, MACHINE_BAREPPC);
360
361 machine_entry_add_alias(me, "bareppc");
362 }
363
364
365 MACHINE_REGISTER(testppc)
366 {
367 MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);
368
369 machine_entry_add_alias(me, "testppc");
370 }
371
372
373 MACHINE_SETUP(baresh)
374 {
375 machine->machine_name = "Generic \"bare\" SH machine";
376 machine->stable = 1;
377 }
378
379
380 MACHINE_SETUP(testsh)
381 {
382 machine->machine_name = "SH test machine";
383 machine->stable = 1;
384
385 /* TODO: interrupt for SH? */
386
387 default_test(machine, cpu);
388 }
389
390
391 MACHINE_DEFAULT_CPU(baresh)
392 {
393 machine->cpu_name = strdup("SH7750");
394 }
395
396
397 MACHINE_DEFAULT_CPU(testsh)
398 {
399 machine->cpu_name = strdup("SH7750");
400 }
401
402
403 MACHINE_REGISTER(baresh)
404 {
405 MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
406 ARCH_SH, MACHINE_BARESH);
407
408 machine_entry_add_alias(me, "baresh");
409 }
410
411
412 MACHINE_REGISTER(testsh)
413 {
414 MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);
415
416 machine_entry_add_alias(me, "testsh");
417 }
418
419
420 MACHINE_SETUP(baresparc)
421 {
422 machine->machine_name = "Generic \"bare\" SPARC machine";
423 machine->stable = 1;
424 }
425
426
427 MACHINE_SETUP(testsparc)
428 {
429 machine->machine_name = "SPARC test machine";
430 machine->stable = 1;
431
432 /* TODO: interrupt for SPARC? */
433
434 default_test(machine, cpu);
435 }
436
437
438 MACHINE_DEFAULT_CPU(baresparc)
439 {
440 machine->cpu_name = strdup("UltraSPARC");
441 }
442
443
444 MACHINE_DEFAULT_CPU(testsparc)
445 {
446 machine->cpu_name = strdup("UltraSPARC");
447 }
448
449
450 MACHINE_REGISTER(baresparc)
451 {
452 MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
453 ARCH_SPARC, MACHINE_BARESPARC);
454
455 machine_entry_add_alias(me, "baresparc");
456 }
457
458
459 MACHINE_REGISTER(testsparc)
460 {
461 MR_DEFAULT(testsparc, "Test-machine for SPARC",
462 ARCH_SPARC, MACHINE_TESTSPARC);
463
464 machine_entry_add_alias(me, "testsparc");
465 }
466
467
468 MACHINE_SETUP(baretransputer)
469 {
470 machine->machine_name = "Generic \"bare\" Transputer machine";
471 machine->stable = 1;
472 }
473
474
475 MACHINE_DEFAULT_CPU(baretransputer)
476 {
477 machine->cpu_name = strdup("T800");
478 }
479
480
481 MACHINE_REGISTER(baretransputer)
482 {
483 MR_DEFAULT(baretransputer, "Generic \"bare\" Transputer machine",
484 ARCH_TRANSPUTER, MACHINE_BARETRANSPUTER);
485
486 machine_entry_add_alias(me, "baretransputer");
487 }
488
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