src/machines/machine_test.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: machine_test.c,v 1.38 2007/06/15 18:08:10 debug Exp $
 *
 *  COMMENT: Various test machines
 *
 *  Generally, the machines are as follows:
 *
 *      bareXYZ:        A bare machine using an XYZ processor.
 *
 *      testXYZ:        A machine with an XYZ processor, and some experimental
 *                      devices connected to it.
 *
 *  The experimental devices in the test machines are:
 *
 *      cons            A serial I/O console device.
 *      disk            A device for reading/writing (emulated) disk sectors.
 *      ether           An ethernet device, for sending/receiving ethernet
 *                      frames on an emulated network.
 *      fb              Framebuffer (24-bit RGB per pixel).
 *      irqc            A generic interrupt controller.
 *      mp              A multiprocessor controller.
 *      rtc             A real-time clock device.
 */

#include <stdio.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "sh4_exception.h"

#include "testmachine/dev_cons.h"
#include "testmachine/dev_disk.h"
#include "testmachine/dev_ether.h"
#include "testmachine/dev_fb.h"
#include "testmachine/dev_irqc.h"
#include "testmachine/dev_mp.h"
#include "testmachine/dev_rtc.h"


/*
 *  default_test():
 *
 *  Initializes devices for most test machines. (Note: MIPS is different,
 *  because of legacy reasons.)
 */
static void default_test(struct machine *machine, struct cpu *cpu)
{
        char tmpstr[1000];
        char base_irq[1000];
        char end_of_base_irq[50];

        /*
         *  First add the interrupt controller. Most processor architectures
         *  in GXemul have only 1 interrupt pin on the CPU, and it is simply
         *  called "emul[x].machine[y].cpu[z]".
         *
         *  MIPS is an exception, dealt with in a separate setup function.
         *  ARM and SH are dealt with here.
         */

        switch (machine->arch) {

        case ARCH_ARM:
                snprintf(end_of_base_irq, sizeof(end_of_base_irq), ".irq");
                break;

        case ARCH_SH:
                snprintf(end_of_base_irq, sizeof(end_of_base_irq),
                    ".irq[0x%x]", SH4_INTEVT_IRQ15);
                break;

        default:
                end_of_base_irq[0] = '\0';
        }

        snprintf(base_irq, sizeof(base_irq), "%s.cpu[%i]%s",
            machine->path, machine->bootstrap_cpu, end_of_base_irq);

        snprintf(tmpstr, sizeof(tmpstr), "irqc addr=0x%"PRIx64" irq=%s",
            (uint64_t) DEV_IRQC_ADDRESS, base_irq);
        device_add(machine, tmpstr);


        /*  Now, add the other devices:  */

        snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64
            " irq=%s.irqc.2 in_use=%i",
            (uint64_t) DEV_CONS_ADDRESS, base_irq, machine->arch != ARCH_SH);
        machine->main_console_handle = (size_t)device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64" irq=%s%sirqc.6",
            (uint64_t) DEV_MP_ADDRESS,
            end_of_base_irq[0]? end_of_base_irq + 1 : "",
            end_of_base_irq[0]? "." : "");
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
            (uint64_t) DEV_FBCTRL_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
            (uint64_t) DEV_DISK_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s.irqc.3",
            (uint64_t) DEV_ETHER_ADDRESS, base_irq);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s.irqc.4",
            (uint64_t) DEV_RTC_ADDRESS, base_irq);
        device_add(machine, tmpstr);
}


MACHINE_SETUP(barealpha)
{
        machine->machine_name = "Generic \"bare\" Alpha machine";
}


MACHINE_SETUP(testalpha)
{
        machine->machine_name = "Alpha test machine";

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(barealpha)
{
        machine->cpu_name = strdup("21264");
}


MACHINE_DEFAULT_CPU(testalpha)
{
        machine->cpu_name = strdup("21264");
}


MACHINE_REGISTER(barealpha)
{
        MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
            ARCH_ALPHA, MACHINE_BAREALPHA);

        machine_entry_add_alias(me, "barealpha");
}


MACHINE_REGISTER(testalpha)
{
        MR_DEFAULT(testalpha, "Test-machine for Alpha",
            ARCH_ALPHA, MACHINE_TESTALPHA);

        machine_entry_add_alias(me, "testalpha");
}


MACHINE_SETUP(barearm)
{
        machine->machine_name = "Generic \"bare\" ARM machine";
}


MACHINE_SETUP(testarm)
{
        machine->machine_name = "ARM test machine";

        default_test(machine, cpu);

        /*
         *  Place a tiny stub at end of memory, and set the link register to
         *  point to it. This stub halts the machine (making it easy to try
         *  out simple stand-alone C functions).
         */
        cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
        cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
        store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
        store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
        store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
}


MACHINE_DEFAULT_CPU(barearm)
{
        machine->cpu_name = strdup("SA1110");
}


MACHINE_DEFAULT_CPU(testarm)
{
        machine->cpu_name = strdup("SA1110");
}


MACHINE_REGISTER(barearm)
{
        MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
            ARCH_ARM, MACHINE_BAREARM);

        machine_entry_add_alias(me, "barearm");
}


MACHINE_REGISTER(testarm)
{
        MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);

        machine_entry_add_alias(me, "testarm");
}


MACHINE_SETUP(barem88k)
{
        machine->machine_name = "Generic \"bare\" M88K machine";
}


MACHINE_SETUP(testm88k)
{
        machine->machine_name = "M88K test machine";

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(barem88k)
{
        machine->cpu_name = strdup("88110");
}


MACHINE_DEFAULT_CPU(testm88k)
{
        machine->cpu_name = strdup("88110");
}


MACHINE_REGISTER(barem88k)
{
        MR_DEFAULT(barem88k, "Generic \"bare\" M88K machine",
            ARCH_M88K, MACHINE_BAREM88K);

        machine_entry_add_alias(me, "barem88k");
}


MACHINE_REGISTER(testm88k)
{
        MR_DEFAULT(testm88k, "Test-machine for M88K",
            ARCH_M88K, MACHINE_TESTM88K);

        machine_entry_add_alias(me, "testm88k");
}


MACHINE_SETUP(baremips)
{
        machine->machine_name = "Generic \"bare\" MIPS machine";
        cpu->byte_order = EMUL_BIG_ENDIAN;
}


MACHINE_SETUP(testmips)
{
        /*
         *  A MIPS test machine. Originally, this was created as a way for
         *  me to test my master's thesis code; since then it has both
         *  evolved to support new things, and suffered bit rot so that it
         *  no longer can run my thesis code. Well, well...
         *
         *  IRQ map:
         *      7       CPU counter
         *      6       SMP IPIs
         *      5       not used yet
         *      4       rtc
         *      3       ethernet  
         *      2       serial console
         */

        char tmpstr[300];

        machine->machine_name = "MIPS test machine";
        cpu->byte_order = EMUL_BIG_ENDIAN;

        snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=%s."
            "cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
            machine->bootstrap_cpu);
        machine->main_console_handle = (size_t)device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64" irq=6",
            (uint64_t) DEV_MP_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
            (uint64_t) DEV_FBCTRL_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
            (uint64_t) DEV_DISK_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s."
            "cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
            machine->bootstrap_cpu);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s."
            "cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
            machine->bootstrap_cpu);
        device_add(machine, tmpstr);
}


MACHINE_DEFAULT_CPU(baremips)
{
        machine->cpu_name = strdup("5KE");
}


MACHINE_DEFAULT_CPU(testmips)
{
        machine->cpu_name = strdup("5KE");
}


MACHINE_REGISTER(baremips)
{
        MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
            ARCH_MIPS, MACHINE_BAREMIPS);

        machine_entry_add_alias(me, "baremips");
}


MACHINE_REGISTER(testmips)
{
        MR_DEFAULT(testmips, "Test-machine for MIPS",
            ARCH_MIPS, MACHINE_TESTMIPS);

        machine_entry_add_alias(me, "testmips");
}


MACHINE_SETUP(bareppc)
{
        machine->machine_name = "Generic \"bare\" PPC machine";
}


MACHINE_SETUP(testppc)
{
        machine->machine_name = "PPC test machine";

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(bareppc)
{
        machine->cpu_name = strdup("PPC970");
}


MACHINE_DEFAULT_CPU(testppc)
{
        machine->cpu_name = strdup("PPC970");
}


MACHINE_REGISTER(bareppc)
{
        MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
            ARCH_PPC, MACHINE_BAREPPC);

        machine_entry_add_alias(me, "bareppc");
}


MACHINE_REGISTER(testppc)
{
        MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);

        machine_entry_add_alias(me, "testppc");
}


MACHINE_SETUP(baresh)
{
        machine->machine_name = "Generic \"bare\" SH machine";
}


MACHINE_SETUP(testsh)
{
        machine->machine_name = "SH test machine";

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(baresh)
{
        machine->cpu_name = strdup("SH7750");
}


MACHINE_DEFAULT_CPU(testsh)
{
        machine->cpu_name = strdup("SH7750");
}


MACHINE_REGISTER(baresh)
{
        MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
            ARCH_SH, MACHINE_BARESH);

        machine_entry_add_alias(me, "baresh");
}


MACHINE_REGISTER(testsh)
{
        MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);

        machine_entry_add_alias(me, "testsh");
}


MACHINE_SETUP(baresparc)
{
        machine->machine_name = "Generic \"bare\" SPARC machine";
}


MACHINE_SETUP(testsparc)
{
        machine->machine_name = "SPARC test machine";

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(baresparc)
{
        machine->cpu_name = strdup("UltraSPARC");
}


MACHINE_DEFAULT_CPU(testsparc)
{
        machine->cpu_name = strdup("UltraSPARC");
}


MACHINE_REGISTER(baresparc)
{
        MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
            ARCH_SPARC, MACHINE_BARESPARC);

        machine_entry_add_alias(me, "baresparc");
}


MACHINE_REGISTER(testsparc)
{
        MR_DEFAULT(testsparc, "Test-machine for SPARC",
            ARCH_SPARC, MACHINE_TESTSPARC);

        machine_entry_add_alias(me, "testsparc");
}


1	/*
2	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: machine_test.c,v 1.38 2007/06/15 18:08:10 debug Exp $
29	*
30	* COMMENT: Various test machines
31	*
32	* Generally, the machines are as follows:
33	*
34	* bareXYZ: A bare machine using an XYZ processor.
35	*
36	* testXYZ: A machine with an XYZ processor, and some experimental
37	* devices connected to it.
38	*
39	* The experimental devices in the test machines are:
40	*
41	* cons A serial I/O console device.
42	* disk A device for reading/writing (emulated) disk sectors.
43	* ether An ethernet device, for sending/receiving ethernet
44	* frames on an emulated network.
45	* fb Framebuffer (24-bit RGB per pixel).
46	* irqc A generic interrupt controller.
47	* mp A multiprocessor controller.
48	* rtc A real-time clock device.
49	*/
50
51	#include <stdio.h>
52	#include <string.h>
53
54	#include "cpu.h"
55	#include "device.h"
56	#include "machine.h"
57	#include "memory.h"
58	#include "misc.h"
59
60	#include "sh4_exception.h"
61
62	#include "testmachine/dev_cons.h"
63	#include "testmachine/dev_disk.h"
64	#include "testmachine/dev_ether.h"
65	#include "testmachine/dev_fb.h"
66	#include "testmachine/dev_irqc.h"
67	#include "testmachine/dev_mp.h"
68	#include "testmachine/dev_rtc.h"
69
70
71	/*
72	* default_test():
73	*
74	* Initializes devices for most test machines. (Note: MIPS is different,
75	* because of legacy reasons.)
76	*/
77	static void default_test(struct machine machine, struct cpu cpu)
78	{
79	char tmpstr[1000];
80	char base_irq[1000];
81	char end_of_base_irq[50];
82
83	/*
84	* First add the interrupt controller. Most processor architectures
85	* in GXemul have only 1 interrupt pin on the CPU, and it is simply
86	* called "emul[x].machine[y].cpu[z]".
87	*
88	* MIPS is an exception, dealt with in a separate setup function.
89	* ARM and SH are dealt with here.
90	*/
91
92	switch (machine->arch) {
93
94	case ARCH_ARM:
95	snprintf(end_of_base_irq, sizeof(end_of_base_irq), ".irq");
96	break;
97
98	case ARCH_SH:
99	snprintf(end_of_base_irq, sizeof(end_of_base_irq),
100	".irq[0x%x]", SH4_INTEVT_IRQ15);
101	break;
102
103	default:
104	end_of_base_irq[0] = '\0';
105	}
106
107	snprintf(base_irq, sizeof(base_irq), "%s.cpu[%i]%s",
108	machine->path, machine->bootstrap_cpu, end_of_base_irq);
109
110	snprintf(tmpstr, sizeof(tmpstr), "irqc addr=0x%"PRIx64" irq=%s",
111	(uint64_t) DEV_IRQC_ADDRESS, base_irq);
112	device_add(machine, tmpstr);
113
114
115	/* Now, add the other devices: */
116
117	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64
118	" irq=%s.irqc.2 in_use=%i",
119	(uint64_t) DEV_CONS_ADDRESS, base_irq, machine->arch != ARCH_SH);
120	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
121
122	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64" irq=%s%sirqc.6",
123	(uint64_t) DEV_MP_ADDRESS,
124	end_of_base_irq[0]? end_of_base_irq + 1 : "",
125	end_of_base_irq[0]? "." : "");
126	device_add(machine, tmpstr);
127
128	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
129	(uint64_t) DEV_FBCTRL_ADDRESS);
130	device_add(machine, tmpstr);
131
132	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
133	(uint64_t) DEV_DISK_ADDRESS);
134	device_add(machine, tmpstr);
135
136	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s.irqc.3",
137	(uint64_t) DEV_ETHER_ADDRESS, base_irq);
138	device_add(machine, tmpstr);
139
140	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s.irqc.4",
141	(uint64_t) DEV_RTC_ADDRESS, base_irq);
142	device_add(machine, tmpstr);
143	}
144
145
146	MACHINE_SETUP(barealpha)
147	{
148	machine->machine_name = "Generic \"bare\" Alpha machine";
149	}
150
151
152	MACHINE_SETUP(testalpha)
153	{
154	machine->machine_name = "Alpha test machine";
155
156	default_test(machine, cpu);
157	}
158
159
160	MACHINE_DEFAULT_CPU(barealpha)
161	{
162	machine->cpu_name = strdup("21264");
163	}
164
165
166	MACHINE_DEFAULT_CPU(testalpha)
167	{
168	machine->cpu_name = strdup("21264");
169	}
170
171
172	MACHINE_REGISTER(barealpha)
173	{
174	MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
175	ARCH_ALPHA, MACHINE_BAREALPHA);
176
177	machine_entry_add_alias(me, "barealpha");
178	}
179
180
181	MACHINE_REGISTER(testalpha)
182	{
183	MR_DEFAULT(testalpha, "Test-machine for Alpha",
184	ARCH_ALPHA, MACHINE_TESTALPHA);
185
186	machine_entry_add_alias(me, "testalpha");
187	}
188
189
190	MACHINE_SETUP(barearm)
191	{
192	machine->machine_name = "Generic \"bare\" ARM machine";
193	}
194
195
196	MACHINE_SETUP(testarm)
197	{
198	machine->machine_name = "ARM test machine";
199
200	default_test(machine, cpu);
201
202	/*
203	* Place a tiny stub at end of memory, and set the link register to
204	* point to it. This stub halts the machine (making it easy to try
205	* out simple stand-alone C functions).
206	*/
207	cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
208	cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
209	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
210	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
211	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
212	}
213
214
215	MACHINE_DEFAULT_CPU(barearm)
216	{
217	machine->cpu_name = strdup("SA1110");
218	}
219
220
221	MACHINE_DEFAULT_CPU(testarm)
222	{
223	machine->cpu_name = strdup("SA1110");
224	}
225
226
227	MACHINE_REGISTER(barearm)
228	{
229	MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
230	ARCH_ARM, MACHINE_BAREARM);
231
232	machine_entry_add_alias(me, "barearm");
233	}
234
235
236	MACHINE_REGISTER(testarm)
237	{
238	MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);
239
240	machine_entry_add_alias(me, "testarm");
241	}
242
243
244
245	MACHINE_SETUP(barem88k)
246	{
247	machine->machine_name = "Generic \"bare\" M88K machine";
248	}
249
250
251	MACHINE_SETUP(testm88k)
252	{
253	machine->machine_name = "M88K test machine";
254
255	default_test(machine, cpu);
256	}
257
258
259	MACHINE_DEFAULT_CPU(barem88k)
260	{
261	machine->cpu_name = strdup("88110");
262	}
263
264
265	MACHINE_DEFAULT_CPU(testm88k)
266	{
267	machine->cpu_name = strdup("88110");
268	}
269
270
271	MACHINE_REGISTER(barem88k)
272	{
273	MR_DEFAULT(barem88k, "Generic \"bare\" M88K machine",
274	ARCH_M88K, MACHINE_BAREM88K);
275
276	machine_entry_add_alias(me, "barem88k");
277	}
278
279
280	MACHINE_REGISTER(testm88k)
281	{
282	MR_DEFAULT(testm88k, "Test-machine for M88K",
283	ARCH_M88K, MACHINE_TESTM88K);
284
285	machine_entry_add_alias(me, "testm88k");
286	}
287
288
289	MACHINE_SETUP(baremips)
290	{
291	machine->machine_name = "Generic \"bare\" MIPS machine";
292	cpu->byte_order = EMUL_BIG_ENDIAN;
293	}
294
295
296	MACHINE_SETUP(testmips)
297	{
298	/*
299	* A MIPS test machine. Originally, this was created as a way for
300	* me to test my master's thesis code; since then it has both
301	* evolved to support new things, and suffered bit rot so that it
302	* no longer can run my thesis code. Well, well...
303	*
304	* IRQ map:
305	* 7 CPU counter
306	* 6 SMP IPIs
307	* 5 not used yet
308	* 4 rtc
309	* 3 ethernet
310	* 2 serial console
311	*/
312
313	char tmpstr[300];
314
315	machine->machine_name = "MIPS test machine";
316	cpu->byte_order = EMUL_BIG_ENDIAN;
317
318	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=%s."
319	"cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
320	machine->bootstrap_cpu);
321	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
322
323	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64" irq=6",
324	(uint64_t) DEV_MP_ADDRESS);
325	device_add(machine, tmpstr);
326
327	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
328	(uint64_t) DEV_FBCTRL_ADDRESS);
329	device_add(machine, tmpstr);
330
331	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
332	(uint64_t) DEV_DISK_ADDRESS);
333	device_add(machine, tmpstr);
334
335	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s."
336	"cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
337	machine->bootstrap_cpu);
338	device_add(machine, tmpstr);
339
340	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s."
341	"cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
342	machine->bootstrap_cpu);
343	device_add(machine, tmpstr);
344	}
345
346
347	MACHINE_DEFAULT_CPU(baremips)
348	{
349	machine->cpu_name = strdup("5KE");
350	}
351
352
353	MACHINE_DEFAULT_CPU(testmips)
354	{
355	machine->cpu_name = strdup("5KE");
356	}
357
358
359	MACHINE_REGISTER(baremips)
360	{
361	MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
362	ARCH_MIPS, MACHINE_BAREMIPS);
363
364	machine_entry_add_alias(me, "baremips");
365	}
366
367
368	MACHINE_REGISTER(testmips)
369	{
370	MR_DEFAULT(testmips, "Test-machine for MIPS",
371	ARCH_MIPS, MACHINE_TESTMIPS);
372
373	machine_entry_add_alias(me, "testmips");
374	}
375
376
377	MACHINE_SETUP(bareppc)
378	{
379	machine->machine_name = "Generic \"bare\" PPC machine";
380	}
381
382
383	MACHINE_SETUP(testppc)
384	{
385	machine->machine_name = "PPC test machine";
386
387	default_test(machine, cpu);
388	}
389
390
391	MACHINE_DEFAULT_CPU(bareppc)
392	{
393	machine->cpu_name = strdup("PPC970");
394	}
395
396
397	MACHINE_DEFAULT_CPU(testppc)
398	{
399	machine->cpu_name = strdup("PPC970");
400	}
401
402
403	MACHINE_REGISTER(bareppc)
404	{
405	MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
406	ARCH_PPC, MACHINE_BAREPPC);
407
408	machine_entry_add_alias(me, "bareppc");
409	}
410
411
412	MACHINE_REGISTER(testppc)
413	{
414	MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);
415
416	machine_entry_add_alias(me, "testppc");
417	}
418
419
420	MACHINE_SETUP(baresh)
421	{
422	machine->machine_name = "Generic \"bare\" SH machine";
423	}
424
425
426	MACHINE_SETUP(testsh)
427	{
428	machine->machine_name = "SH test machine";
429
430	default_test(machine, cpu);
431	}
432
433
434	MACHINE_DEFAULT_CPU(baresh)
435	{
436	machine->cpu_name = strdup("SH7750");
437	}
438
439
440	MACHINE_DEFAULT_CPU(testsh)
441	{
442	machine->cpu_name = strdup("SH7750");
443	}
444
445
446	MACHINE_REGISTER(baresh)
447	{
448	MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
449	ARCH_SH, MACHINE_BARESH);
450
451	machine_entry_add_alias(me, "baresh");
452	}
453
454
455	MACHINE_REGISTER(testsh)
456	{
457	MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);
458
459	machine_entry_add_alias(me, "testsh");
460	}
461
462
463	MACHINE_SETUP(baresparc)
464	{
465	machine->machine_name = "Generic \"bare\" SPARC machine";
466	}
467
468
469	MACHINE_SETUP(testsparc)
470	{
471	machine->machine_name = "SPARC test machine";
472
473	default_test(machine, cpu);
474	}
475
476
477	MACHINE_DEFAULT_CPU(baresparc)
478	{
479	machine->cpu_name = strdup("UltraSPARC");
480	}
481
482
483	MACHINE_DEFAULT_CPU(testsparc)
484	{
485	machine->cpu_name = strdup("UltraSPARC");
486	}
487
488
489	MACHINE_REGISTER(baresparc)
490	{
491	MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
492	ARCH_SPARC, MACHINE_BARESPARC);
493
494	machine_entry_add_alias(me, "baresparc");
495	}
496
497
498	MACHINE_REGISTER(testsparc)
499	{
500	MR_DEFAULT(testsparc, "Test-machine for SPARC",
501	ARCH_SPARC, MACHINE_TESTSPARC);
502
503	machine_entry_add_alias(me, "testsparc");
504	}
505
506