src/machines/machine_test.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: machine_test.c,v 1.31 2007/04/10 17:26:20 debug Exp $
 *
 *  Various "test" machines (bare machines with just a CPU, or a bare machine
 *  plus some experimental devices).
 */

#include <stdio.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "testmachine/dev_cons.h"
#include "testmachine/dev_disk.h"
#include "testmachine/dev_ether.h"
#include "testmachine/dev_fb.h"
#include "testmachine/dev_mp.h"
#include "testmachine/dev_rtc.h"


static void default_test(struct machine *machine, struct cpu *cpu)
{
        char tmpstr[1000];

        snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=none",
            (uint64_t) DEV_CONS_ADDRESS);
        machine->main_console_handle = (size_t)device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
            (uint64_t) DEV_MP_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
            (uint64_t) DEV_FBCTRL_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
            (uint64_t) DEV_DISK_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=none",
            (uint64_t) DEV_ETHER_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=none",
            (uint64_t) DEV_RTC_ADDRESS);
        device_add(machine, tmpstr);
}


MACHINE_SETUP(barealpha)
{
        machine->machine_name = "Generic \"bare\" Alpha machine";
        machine->stable = 1;
}


MACHINE_SETUP(testalpha)
{
        machine->machine_name = "Alpha test machine";
        machine->stable = 1;

        /*  TODO: interrupt for Alpha?  */

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(barealpha)
{
        machine->cpu_name = strdup("21264");
}


MACHINE_DEFAULT_CPU(testalpha)
{
        machine->cpu_name = strdup("21264");
}


MACHINE_REGISTER(barealpha)
{
        MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
            ARCH_ALPHA, MACHINE_BAREALPHA);

        machine_entry_add_alias(me, "barealpha");
}


MACHINE_REGISTER(testalpha)
{
        MR_DEFAULT(testalpha, "Test-machine for Alpha",
            ARCH_ALPHA, MACHINE_TESTALPHA);

        machine_entry_add_alias(me, "testalpha");
}


MACHINE_SETUP(barearm)
{
        machine->machine_name = "Generic \"bare\" ARM machine";
        machine->stable = 1;
}


MACHINE_SETUP(testarm)
{
        machine->machine_name = "ARM test machine";
        machine->stable = 1;

        /*  TODO: interrupt for ARM?  */

        default_test(machine, cpu);

        /*
         *  Place a tiny stub at end of memory, and set the link register to
         *  point to it. This stub halts the machine (making it easy to try
         *  out simple stand-alone C functions).
         */
        cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
        cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
        store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
        store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
        store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
}


MACHINE_DEFAULT_CPU(barearm)
{
        machine->cpu_name = strdup("SA1110");
}


MACHINE_DEFAULT_CPU(testarm)
{
        machine->cpu_name = strdup("SA1110");
}


MACHINE_REGISTER(barearm)
{
        MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
            ARCH_ARM, MACHINE_BAREARM);

        machine_entry_add_alias(me, "barearm");
}


MACHINE_REGISTER(testarm)
{
        MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);

        machine_entry_add_alias(me, "testarm");
}


MACHINE_SETUP(barem68k)
{
        machine->machine_name = "Generic \"bare\" M68K machine";
        machine->stable = 1;
}


MACHINE_SETUP(testm68k)
{
        machine->machine_name = "M68K test machine";
        machine->stable = 1;

        /*  TODO: interrupt for M68K?  */

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(barem68k)
{
        machine->cpu_name = strdup("68020");
}


MACHINE_DEFAULT_CPU(testm68k)
{
        machine->cpu_name = strdup("68020");
}


MACHINE_REGISTER(barem68k)
{
        MR_DEFAULT(barem68k, "Generic \"bare\" M68K machine",
            ARCH_M68K, MACHINE_BAREM68K);

        machine_entry_add_alias(me, "barem68k");
}


MACHINE_REGISTER(testm68k)
{
        MR_DEFAULT(testm68k, "Test-machine for M68K",
            ARCH_M68K, MACHINE_TESTM68K);

        machine_entry_add_alias(me, "testm68k");
}


MACHINE_SETUP(baremips)
{
        machine->machine_name = "Generic \"bare\" MIPS machine";
        machine->stable = 1;
        cpu->byte_order = EMUL_BIG_ENDIAN;
}


MACHINE_SETUP(testmips)
{
        /*
         *  A MIPS test machine. Originally, this was created as a way for
         *  me to test my master's thesis code; since then it has both
         *  evolved to support new things, and suffered bit rot so that it
         *  no longer can run my thesis code. Well, well...
         *
         *  IRQ map:
         *      7       CPU counter
         *      6       SMP IPIs
         *      5       not used yet
         *      4       rtc
         *      3       ethernet  
         *      2       serial console
         */

        char tmpstr[300];

        machine->machine_name = "MIPS test machine";
        machine->stable = 1;
        cpu->byte_order = EMUL_BIG_ENDIAN;

        snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=%s."
            "cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
            machine->bootstrap_cpu);
        machine->main_console_handle = (size_t)device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "mp irq=6 addr=0x%"PRIx64,
            (uint64_t) DEV_MP_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
            (uint64_t) DEV_FBCTRL_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
            (uint64_t) DEV_DISK_ADDRESS);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s."
            "cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
            machine->bootstrap_cpu);
        device_add(machine, tmpstr);

        snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s."
            "cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
            machine->bootstrap_cpu);
        device_add(machine, tmpstr);
}


MACHINE_DEFAULT_CPU(baremips)
{
        machine->cpu_name = strdup("5KE");
}


MACHINE_DEFAULT_CPU(testmips)
{
        machine->cpu_name = strdup("5KE");
}


MACHINE_REGISTER(baremips)
{
        MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
            ARCH_MIPS, MACHINE_BAREMIPS);

        machine_entry_add_alias(me, "baremips");
}


MACHINE_REGISTER(testmips)
{
        MR_DEFAULT(testmips, "Test-machine for MIPS",
            ARCH_MIPS, MACHINE_TESTMIPS);

        machine_entry_add_alias(me, "testmips");
}


MACHINE_SETUP(bareppc)
{
        machine->machine_name = "Generic \"bare\" PPC machine";
        machine->stable = 1;
}


MACHINE_SETUP(testppc)
{
        machine->machine_name = "PPC test machine";
        machine->stable = 1;

        /*  TODO: interrupt for PPC?  */

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(bareppc)
{
        machine->cpu_name = strdup("PPC970");
}


MACHINE_DEFAULT_CPU(testppc)
{
        machine->cpu_name = strdup("PPC970");
}


MACHINE_REGISTER(bareppc)
{
        MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
            ARCH_PPC, MACHINE_BAREPPC);

        machine_entry_add_alias(me, "bareppc");
}


MACHINE_REGISTER(testppc)
{
        MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);

        machine_entry_add_alias(me, "testppc");
}


MACHINE_SETUP(baresh)
{
        machine->machine_name = "Generic \"bare\" SH machine";
        machine->stable = 1;
}


MACHINE_SETUP(testsh)
{
        machine->machine_name = "SH test machine";
        machine->stable = 1;

        /*  TODO: interrupt for SH?  */

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(baresh)
{
        machine->cpu_name = strdup("SH7750");
}


MACHINE_DEFAULT_CPU(testsh)
{
        machine->cpu_name = strdup("SH7750");
}


MACHINE_REGISTER(baresh)
{
        MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
            ARCH_SH, MACHINE_BARESH);

        machine_entry_add_alias(me, "baresh");
}


MACHINE_REGISTER(testsh)
{
        MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);

        machine_entry_add_alias(me, "testsh");
}


MACHINE_SETUP(baresparc)
{
        machine->machine_name = "Generic \"bare\" SPARC machine";
        machine->stable = 1;
}


MACHINE_SETUP(testsparc)
{
        machine->machine_name = "SPARC test machine";
        machine->stable = 1;

        /*  TODO: interrupt for SPARC?  */

        default_test(machine, cpu);
}


MACHINE_DEFAULT_CPU(baresparc)
{
        machine->cpu_name = strdup("UltraSPARC");
}


MACHINE_DEFAULT_CPU(testsparc)
{
        machine->cpu_name = strdup("UltraSPARC");
}


MACHINE_REGISTER(baresparc)
{
        MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
            ARCH_SPARC, MACHINE_BARESPARC);

        machine_entry_add_alias(me, "baresparc");
}


MACHINE_REGISTER(testsparc)
{
        MR_DEFAULT(testsparc, "Test-machine for SPARC",
            ARCH_SPARC, MACHINE_TESTSPARC);

        machine_entry_add_alias(me, "testsparc");
}


1	dpavlin	22	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	22	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	38	* $Id: machine_test.c,v 1.31 2007/04/10 17:26:20 debug Exp $
29	dpavlin	22	*
30			* Various "test" machines (bare machines with just a CPU, or a bare machine
31			* plus some experimental devices).
32			*/
33
34			#include <stdio.h>
35			#include <string.h>
36
37			#include "cpu.h"
38			#include "device.h"
39			#include "machine.h"
40			#include "memory.h"
41			#include "misc.h"
42
43	dpavlin	24	#include "testmachine/dev_cons.h"
44			#include "testmachine/dev_disk.h"
45			#include "testmachine/dev_ether.h"
46			#include "testmachine/dev_fb.h"
47			#include "testmachine/dev_mp.h"
48	dpavlin	32	#include "testmachine/dev_rtc.h"
49	dpavlin	22
50	dpavlin	24
51	dpavlin	22	static void default_test(struct machine machine, struct cpu cpu)
52			{
53			char tmpstr[1000];
54	dpavlin	24
55	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=none",
56	dpavlin	24	(uint64_t) DEV_CONS_ADDRESS);
57	dpavlin	22	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
58
59	dpavlin	24	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
60			(uint64_t) DEV_MP_ADDRESS);
61	dpavlin	22	device_add(machine, tmpstr);
62
63	dpavlin	28	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
64			(uint64_t) DEV_FBCTRL_ADDRESS);
65			device_add(machine, tmpstr);
66	dpavlin	22
67	dpavlin	24	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
68			(uint64_t) DEV_DISK_ADDRESS);
69	dpavlin	22	device_add(machine, tmpstr);
70
71	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=none",
72	dpavlin	24	(uint64_t) DEV_ETHER_ADDRESS);
73	dpavlin	22	device_add(machine, tmpstr);
74	dpavlin	32
75	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=none",
76	dpavlin	32	(uint64_t) DEV_RTC_ADDRESS);
77			device_add(machine, tmpstr);
78	dpavlin	22	}
79
80
81			MACHINE_SETUP(barealpha)
82			{
83			machine->machine_name = "Generic \"bare\" Alpha machine";
84			machine->stable = 1;
85			}
86
87
88			MACHINE_SETUP(testalpha)
89			{
90			machine->machine_name = "Alpha test machine";
91			machine->stable = 1;
92
93			/* TODO: interrupt for Alpha? */
94
95			default_test(machine, cpu);
96			}
97
98
99			MACHINE_DEFAULT_CPU(barealpha)
100			{
101	dpavlin	24	machine->cpu_name = strdup("21264");
102	dpavlin	22	}
103
104
105			MACHINE_DEFAULT_CPU(testalpha)
106			{
107	dpavlin	24	machine->cpu_name = strdup("21264");
108	dpavlin	22	}
109
110
111			MACHINE_REGISTER(barealpha)
112			{
113			MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
114	dpavlin	26	ARCH_ALPHA, MACHINE_BAREALPHA);
115
116			machine_entry_add_alias(me, "barealpha");
117	dpavlin	22	}
118
119
120			MACHINE_REGISTER(testalpha)
121			{
122			MR_DEFAULT(testalpha, "Test-machine for Alpha",
123	dpavlin	26	ARCH_ALPHA, MACHINE_TESTALPHA);
124
125			machine_entry_add_alias(me, "testalpha");
126	dpavlin	22	}
127
128
129			MACHINE_SETUP(barearm)
130			{
131			machine->machine_name = "Generic \"bare\" ARM machine";
132			machine->stable = 1;
133			}
134
135
136			MACHINE_SETUP(testarm)
137			{
138			machine->machine_name = "ARM test machine";
139			machine->stable = 1;
140
141			/* TODO: interrupt for ARM? */
142
143			default_test(machine, cpu);
144
145			/*
146			* Place a tiny stub at end of memory, and set the link register to
147			* point to it. This stub halts the machine (making it easy to try
148			* out simple stand-alone C functions).
149			*/
150			cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
151			cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
152			store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
153			store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
154			store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
155			}
156
157
158			MACHINE_DEFAULT_CPU(barearm)
159			{
160			machine->cpu_name = strdup("SA1110");
161			}
162
163
164			MACHINE_DEFAULT_CPU(testarm)
165			{
166			machine->cpu_name = strdup("SA1110");
167			}
168
169
170			MACHINE_REGISTER(barearm)
171			{
172			MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
173	dpavlin	26	ARCH_ARM, MACHINE_BAREARM);
174
175			machine_entry_add_alias(me, "barearm");
176	dpavlin	22	}
177
178
179			MACHINE_REGISTER(testarm)
180			{
181	dpavlin	26	MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);
182
183			machine_entry_add_alias(me, "testarm");
184	dpavlin	22	}
185
186
187
188			MACHINE_SETUP(barem68k)
189			{
190			machine->machine_name = "Generic \"bare\" M68K machine";
191			machine->stable = 1;
192			}
193
194
195			MACHINE_SETUP(testm68k)
196			{
197			machine->machine_name = "M68K test machine";
198			machine->stable = 1;
199
200			/* TODO: interrupt for M68K? */
201
202			default_test(machine, cpu);
203			}
204
205
206			MACHINE_DEFAULT_CPU(barem68k)
207			{
208			machine->cpu_name = strdup("68020");
209			}
210
211
212			MACHINE_DEFAULT_CPU(testm68k)
213			{
214			machine->cpu_name = strdup("68020");
215			}
216
217
218			MACHINE_REGISTER(barem68k)
219			{
220			MR_DEFAULT(barem68k, "Generic \"bare\" M68K machine",
221	dpavlin	26	ARCH_M68K, MACHINE_BAREM68K);
222
223			machine_entry_add_alias(me, "barem68k");
224	dpavlin	22	}
225
226
227			MACHINE_REGISTER(testm68k)
228			{
229			MR_DEFAULT(testm68k, "Test-machine for M68K",
230	dpavlin	26	ARCH_M68K, MACHINE_TESTM68K);
231
232			machine_entry_add_alias(me, "testm68k");
233	dpavlin	22	}
234
235
236			MACHINE_SETUP(baremips)
237			{
238			machine->machine_name = "Generic \"bare\" MIPS machine";
239			machine->stable = 1;
240			cpu->byte_order = EMUL_BIG_ENDIAN;
241			}
242
243
244			MACHINE_SETUP(testmips)
245			{
246			/*
247	dpavlin	34	* A MIPS test machine. Originally, this was created as a way for
248			* me to test my master's thesis code; since then it has both
249			* evolved to support new things, and suffered bit rot so that it
250			* no longer can run my thesis code. Well, well...
251	dpavlin	22	*
252			* IRQ map:
253			* 7 CPU counter
254			* 6 SMP IPIs
255			* 5 not used yet
256	dpavlin	32	* 4 rtc
257	dpavlin	22	* 3 ethernet
258			* 2 serial console
259			*/
260
261	dpavlin	34	char tmpstr[300];
262	dpavlin	22
263			machine->machine_name = "MIPS test machine";
264			machine->stable = 1;
265			cpu->byte_order = EMUL_BIG_ENDIAN;
266
267	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=%s."
268			"cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
269			machine->bootstrap_cpu);
270	dpavlin	22	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
271
272	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "mp irq=6 addr=0x%"PRIx64,
273	dpavlin	24	(uint64_t) DEV_MP_ADDRESS);
274	dpavlin	22	device_add(machine, tmpstr);
275
276	dpavlin	28	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
277			(uint64_t) DEV_FBCTRL_ADDRESS);
278			device_add(machine, tmpstr);
279	dpavlin	22
280	dpavlin	24	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
281			(uint64_t) DEV_DISK_ADDRESS);
282	dpavlin	22	device_add(machine, tmpstr);
283
284	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s."
285			"cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
286			machine->bootstrap_cpu);
287	dpavlin	22	device_add(machine, tmpstr);
288	dpavlin	32
289	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s."
290			"cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
291			machine->bootstrap_cpu);
292	dpavlin	32	device_add(machine, tmpstr);
293	dpavlin	22	}
294
295
296			MACHINE_DEFAULT_CPU(baremips)
297			{
298	dpavlin	34	machine->cpu_name = strdup("5KE");
299	dpavlin	22	}
300
301
302			MACHINE_DEFAULT_CPU(testmips)
303			{
304	dpavlin	34	machine->cpu_name = strdup("5KE");
305	dpavlin	22	}
306
307
308			MACHINE_REGISTER(baremips)
309			{
310			MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
311	dpavlin	26	ARCH_MIPS, MACHINE_BAREMIPS);
312
313			machine_entry_add_alias(me, "baremips");
314	dpavlin	22	}
315
316
317			MACHINE_REGISTER(testmips)
318			{
319			MR_DEFAULT(testmips, "Test-machine for MIPS",
320	dpavlin	26	ARCH_MIPS, MACHINE_TESTMIPS);
321
322			machine_entry_add_alias(me, "testmips");
323	dpavlin	22	}
324
325
326			MACHINE_SETUP(bareppc)
327			{
328			machine->machine_name = "Generic \"bare\" PPC machine";
329			machine->stable = 1;
330			}
331
332
333			MACHINE_SETUP(testppc)
334			{
335			machine->machine_name = "PPC test machine";
336			machine->stable = 1;
337
338			/* TODO: interrupt for PPC? */
339
340			default_test(machine, cpu);
341			}
342
343
344			MACHINE_DEFAULT_CPU(bareppc)
345			{
346			machine->cpu_name = strdup("PPC970");
347			}
348
349
350			MACHINE_DEFAULT_CPU(testppc)
351			{
352			machine->cpu_name = strdup("PPC970");
353			}
354
355
356			MACHINE_REGISTER(bareppc)
357			{
358			MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
359	dpavlin	26	ARCH_PPC, MACHINE_BAREPPC);
360
361			machine_entry_add_alias(me, "bareppc");
362	dpavlin	22	}
363
364
365			MACHINE_REGISTER(testppc)
366			{
367	dpavlin	26	MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);
368
369			machine_entry_add_alias(me, "testppc");
370	dpavlin	22	}
371
372
373			MACHINE_SETUP(baresh)
374			{
375			machine->machine_name = "Generic \"bare\" SH machine";
376			machine->stable = 1;
377			}
378
379
380			MACHINE_SETUP(testsh)
381			{
382			machine->machine_name = "SH test machine";
383			machine->stable = 1;
384
385			/* TODO: interrupt for SH? */
386
387			default_test(machine, cpu);
388			}
389
390
391			MACHINE_DEFAULT_CPU(baresh)
392			{
393	dpavlin	32	machine->cpu_name = strdup("SH7750");
394	dpavlin	22	}
395
396
397			MACHINE_DEFAULT_CPU(testsh)
398			{
399	dpavlin	32	machine->cpu_name = strdup("SH7750");
400	dpavlin	22	}
401
402
403			MACHINE_REGISTER(baresh)
404			{
405			MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
406	dpavlin	26	ARCH_SH, MACHINE_BARESH);
407
408			machine_entry_add_alias(me, "baresh");
409	dpavlin	22	}
410
411
412			MACHINE_REGISTER(testsh)
413			{
414	dpavlin	26	MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);
415
416			machine_entry_add_alias(me, "testsh");
417	dpavlin	22	}
418
419
420			MACHINE_SETUP(baresparc)
421			{
422			machine->machine_name = "Generic \"bare\" SPARC machine";
423			machine->stable = 1;
424			}
425
426
427			MACHINE_SETUP(testsparc)
428			{
429			machine->machine_name = "SPARC test machine";
430			machine->stable = 1;
431
432			/* TODO: interrupt for SPARC? */
433
434			default_test(machine, cpu);
435			}
436
437
438			MACHINE_DEFAULT_CPU(baresparc)
439			{
440	dpavlin	24	machine->cpu_name = strdup("UltraSPARC");
441	dpavlin	22	}
442
443
444			MACHINE_DEFAULT_CPU(testsparc)
445			{
446	dpavlin	24	machine->cpu_name = strdup("UltraSPARC");
447	dpavlin	22	}
448
449
450			MACHINE_REGISTER(baresparc)
451			{
452			MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
453	dpavlin	26	ARCH_SPARC, MACHINE_BARESPARC);
454
455			machine_entry_add_alias(me, "baresparc");
456	dpavlin	22	}
457
458
459			MACHINE_REGISTER(testsparc)
460			{
461			MR_DEFAULT(testsparc, "Test-machine for SPARC",
462	dpavlin	26	ARCH_SPARC, MACHINE_TESTSPARC);
463
464			machine_entry_add_alias(me, "testsparc");
465	dpavlin	22	}
466
467	dpavlin	28