/[gxemul]/trunk/src/machines/machine_test.c
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Revision 24 - (hide annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 12272 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 dpavlin 22 /*
2     * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 24 * $Id: machine_test.c,v 1.13 2006/06/12 10:21:12 debug Exp $
29 dpavlin 22 *
30     * Various "test" machines (bare machines with just a CPU, or a bare machine
31     * plus some experimental devices).
32     */
33    
34     #include <stdio.h>
35     #include <string.h>
36    
37     #include "cpu.h"
38     #include "device.h"
39     #include "devices.h"
40     #include "machine.h"
41     #include "memory.h"
42     #include "misc.h"
43    
44 dpavlin 24 #include "testmachine/dev_cons.h"
45     #include "testmachine/dev_disk.h"
46     #include "testmachine/dev_ether.h"
47     #include "testmachine/dev_fb.h"
48     #include "testmachine/dev_mp.h"
49 dpavlin 22
50 dpavlin 24
51 dpavlin 22 static void default_test(struct machine *machine, struct cpu *cpu)
52     {
53     char tmpstr[1000];
54 dpavlin 24
55     snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=0",
56     (uint64_t) DEV_CONS_ADDRESS);
57 dpavlin 22 machine->main_console_handle = (size_t)device_add(machine, tmpstr);
58    
59 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
60     (uint64_t) DEV_MP_ADDRESS);
61 dpavlin 22 device_add(machine, tmpstr);
62    
63     dev_fb_init(machine, machine->memory, DEV_FB_ADDRESS, VFB_GENERIC,
64 dpavlin 24 640,480, 640,480, 24, "generic");
65 dpavlin 22
66 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
67     (uint64_t) DEV_DISK_ADDRESS);
68 dpavlin 22 device_add(machine, tmpstr);
69    
70 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=0",
71     (uint64_t) DEV_ETHER_ADDRESS);
72 dpavlin 22 device_add(machine, tmpstr);
73     }
74    
75    
76     MACHINE_SETUP(barealpha)
77     {
78     machine->machine_name = "Generic \"bare\" Alpha machine";
79     machine->stable = 1;
80     }
81    
82    
83     MACHINE_SETUP(testalpha)
84     {
85     machine->machine_name = "Alpha test machine";
86     machine->stable = 1;
87    
88     /* TODO: interrupt for Alpha? */
89    
90     default_test(machine, cpu);
91     }
92    
93    
94     MACHINE_DEFAULT_CPU(barealpha)
95     {
96 dpavlin 24 machine->cpu_name = strdup("21264");
97 dpavlin 22 }
98    
99    
100     MACHINE_DEFAULT_CPU(testalpha)
101     {
102 dpavlin 24 machine->cpu_name = strdup("21264");
103 dpavlin 22 }
104    
105    
106     MACHINE_REGISTER(barealpha)
107     {
108     MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
109     ARCH_ALPHA, MACHINE_BAREALPHA, 1, 0);
110     me->aliases[0] = "barealpha";
111     machine_entry_add(me, ARCH_ALPHA);
112     }
113    
114    
115     MACHINE_REGISTER(testalpha)
116     {
117     MR_DEFAULT(testalpha, "Test-machine for Alpha",
118     ARCH_ALPHA, MACHINE_TESTALPHA, 1, 0);
119     me->aliases[0] = "testalpha";
120     machine_entry_add(me, ARCH_ALPHA);
121     }
122    
123    
124     MACHINE_SETUP(barearm)
125     {
126     machine->machine_name = "Generic \"bare\" ARM machine";
127     machine->stable = 1;
128     }
129    
130    
131     MACHINE_SETUP(testarm)
132     {
133     machine->machine_name = "ARM test machine";
134     machine->stable = 1;
135    
136     /* TODO: interrupt for ARM? */
137    
138     default_test(machine, cpu);
139    
140     /*
141     * Place a tiny stub at end of memory, and set the link register to
142     * point to it. This stub halts the machine (making it easy to try
143     * out simple stand-alone C functions).
144     */
145     cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
146     cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
147     store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
148     store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
149     store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
150     }
151    
152    
153     MACHINE_DEFAULT_CPU(barearm)
154     {
155     machine->cpu_name = strdup("SA1110");
156     }
157    
158    
159     MACHINE_DEFAULT_CPU(testarm)
160     {
161     machine->cpu_name = strdup("SA1110");
162     }
163    
164    
165     MACHINE_REGISTER(barearm)
166     {
167     MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
168     ARCH_ARM, MACHINE_BAREARM, 1, 0);
169     me->aliases[0] = "barearm";
170     machine_entry_add(me, ARCH_ARM);
171     }
172    
173    
174     MACHINE_REGISTER(testarm)
175     {
176     MR_DEFAULT(testarm, "Test-machine for ARM",
177     ARCH_ARM, MACHINE_TESTARM, 1, 0);
178     me->aliases[0] = "testarm";
179     machine_entry_add(me, ARCH_ARM);
180     }
181    
182    
183    
184     MACHINE_SETUP(barehppa)
185     {
186     machine->machine_name = "Generic \"bare\" HPPA machine";
187     machine->stable = 1;
188     }
189    
190    
191     MACHINE_SETUP(testhppa)
192     {
193     machine->machine_name = "HPPA test machine";
194     machine->stable = 1;
195    
196     /* TODO: interrupt for HPPA? */
197    
198     default_test(machine, cpu);
199     }
200    
201    
202     MACHINE_DEFAULT_CPU(barehppa)
203     {
204     machine->cpu_name = strdup("HPPA");
205     }
206    
207    
208     MACHINE_DEFAULT_CPU(testhppa)
209     {
210     machine->cpu_name = strdup("HPPA");
211     }
212    
213    
214     MACHINE_REGISTER(barehppa)
215     {
216     MR_DEFAULT(barehppa, "Generic \"bare\" HPPA machine",
217     ARCH_HPPA, MACHINE_BAREHPPA, 1, 0);
218     me->aliases[0] = "barehppa";
219     machine_entry_add(me, ARCH_HPPA);
220     }
221    
222    
223     MACHINE_REGISTER(testhppa)
224     {
225     MR_DEFAULT(testhppa, "Test-machine for HPPA",
226     ARCH_HPPA, MACHINE_TESTHPPA, 1, 0);
227     me->aliases[0] = "testhppa";
228     machine_entry_add(me, ARCH_HPPA);
229     }
230    
231    
232     MACHINE_SETUP(barei960)
233     {
234     machine->machine_name = "Generic \"bare\" i960 machine";
235     machine->stable = 1;
236     }
237    
238    
239     MACHINE_SETUP(testi960)
240     {
241     machine->machine_name = "i960 test machine";
242     machine->stable = 1;
243    
244     /* TODO: interrupt for i960? */
245    
246     default_test(machine, cpu);
247     }
248    
249    
250     MACHINE_DEFAULT_CPU(barei960)
251     {
252     machine->cpu_name = strdup("i960");
253     }
254    
255    
256     MACHINE_DEFAULT_CPU(testi960)
257     {
258     machine->cpu_name = strdup("i960");
259     }
260    
261    
262     MACHINE_REGISTER(barei960)
263     {
264     MR_DEFAULT(barei960, "Generic \"bare\" i960 machine",
265     ARCH_I960, MACHINE_BAREI960, 1, 0);
266     me->aliases[0] = "barei960";
267     machine_entry_add(me, ARCH_I960);
268     }
269    
270    
271     MACHINE_REGISTER(testi960)
272     {
273     MR_DEFAULT(testi960, "Test-machine for i960",
274     ARCH_I960, MACHINE_TESTI960, 1, 0);
275     me->aliases[0] = "testi960";
276     machine_entry_add(me, ARCH_I960);
277     }
278    
279    
280     MACHINE_SETUP(bareia64)
281     {
282     machine->machine_name = "Generic \"bare\" IA64 machine";
283     machine->stable = 1;
284     }
285    
286    
287     MACHINE_SETUP(testia64)
288     {
289     machine->machine_name = "IA64 test machine";
290     machine->stable = 1;
291    
292     /* TODO: interrupt for IA64? */
293    
294     default_test(machine, cpu);
295     }
296    
297    
298     MACHINE_DEFAULT_CPU(bareia64)
299     {
300     machine->cpu_name = strdup("IA64");
301     }
302    
303    
304     MACHINE_DEFAULT_CPU(testia64)
305     {
306     machine->cpu_name = strdup("IA64");
307     }
308    
309    
310     MACHINE_REGISTER(bareia64)
311     {
312     MR_DEFAULT(bareia64, "Generic \"bare\" IA64 machine",
313     ARCH_IA64, MACHINE_BAREIA64, 1, 0);
314     me->aliases[0] = "bareia64";
315     machine_entry_add(me, ARCH_IA64);
316     }
317    
318    
319     MACHINE_REGISTER(testia64)
320     {
321     MR_DEFAULT(testia64, "Test-machine for IA64",
322     ARCH_IA64, MACHINE_TESTIA64, 1, 0);
323     me->aliases[0] = "testia64";
324     machine_entry_add(me, ARCH_IA64);
325     }
326    
327    
328     MACHINE_SETUP(barem68k)
329     {
330     machine->machine_name = "Generic \"bare\" M68K machine";
331     machine->stable = 1;
332     }
333    
334    
335     MACHINE_SETUP(testm68k)
336     {
337     machine->machine_name = "M68K test machine";
338     machine->stable = 1;
339    
340     /* TODO: interrupt for M68K? */
341    
342     default_test(machine, cpu);
343     }
344    
345    
346     MACHINE_DEFAULT_CPU(barem68k)
347     {
348     machine->cpu_name = strdup("68020");
349     }
350    
351    
352     MACHINE_DEFAULT_CPU(testm68k)
353     {
354     machine->cpu_name = strdup("68020");
355     }
356    
357    
358     MACHINE_REGISTER(barem68k)
359     {
360     MR_DEFAULT(barem68k, "Generic \"bare\" M68K machine",
361     ARCH_M68K, MACHINE_BAREM68K, 1, 0);
362     me->aliases[0] = "barem68k";
363     machine_entry_add(me, ARCH_M68K);
364     }
365    
366    
367     MACHINE_REGISTER(testm68k)
368     {
369     MR_DEFAULT(testm68k, "Test-machine for M68K",
370     ARCH_M68K, MACHINE_TESTM68K, 1, 0);
371     me->aliases[0] = "testm68k";
372     machine_entry_add(me, ARCH_M68K);
373     }
374    
375    
376     MACHINE_SETUP(baremips)
377     {
378     machine->machine_name = "Generic \"bare\" MIPS machine";
379     machine->stable = 1;
380     cpu->byte_order = EMUL_BIG_ENDIAN;
381     }
382    
383    
384     MACHINE_SETUP(testmips)
385     {
386     /*
387     * A MIPS test machine (which happens to work with the
388     * code in my master's thesis). :-)
389     *
390     * IRQ map:
391     * 7 CPU counter
392     * 6 SMP IPIs
393     * 5 not used yet
394     * 4 not used yet
395     * 3 ethernet
396     * 2 serial console
397     */
398    
399     char tmpstr[1000];
400    
401     machine->machine_name = "MIPS test machine";
402     machine->stable = 1;
403     cpu->byte_order = EMUL_BIG_ENDIAN;
404    
405 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=2",
406     (uint64_t) DEV_CONS_ADDRESS);
407 dpavlin 22 machine->main_console_handle = (size_t)device_add(machine, tmpstr);
408    
409 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64,
410     (uint64_t) DEV_MP_ADDRESS);
411 dpavlin 22 device_add(machine, tmpstr);
412    
413     dev_fb_init(machine, machine->memory, DEV_FB_ADDRESS, VFB_GENERIC,
414     640,480, 640,480, 24, "testmips generic");
415    
416 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
417     (uint64_t) DEV_DISK_ADDRESS);
418 dpavlin 22 device_add(machine, tmpstr);
419    
420 dpavlin 24 snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=3",
421     (uint64_t) DEV_ETHER_ADDRESS);
422 dpavlin 22 device_add(machine, tmpstr);
423     }
424    
425    
426     MACHINE_DEFAULT_CPU(baremips)
427     {
428 dpavlin 24 machine->cpu_name = strdup("5Kc");
429 dpavlin 22 }
430    
431    
432     MACHINE_DEFAULT_CPU(testmips)
433     {
434 dpavlin 24 machine->cpu_name = strdup("5Kc");
435 dpavlin 22 }
436    
437    
438     MACHINE_REGISTER(baremips)
439     {
440     MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
441     ARCH_MIPS, MACHINE_BAREMIPS, 1, 0);
442     me->aliases[0] = "baremips";
443     machine_entry_add(me, ARCH_MIPS);
444     }
445    
446    
447     MACHINE_REGISTER(testmips)
448     {
449     MR_DEFAULT(testmips, "Test-machine for MIPS",
450     ARCH_MIPS, MACHINE_TESTMIPS, 1, 0);
451     me->aliases[0] = "testmips";
452     machine_entry_add(me, ARCH_MIPS);
453     }
454    
455    
456     MACHINE_SETUP(bareppc)
457     {
458     machine->machine_name = "Generic \"bare\" PPC machine";
459     machine->stable = 1;
460     }
461    
462    
463     MACHINE_SETUP(testppc)
464     {
465     machine->machine_name = "PPC test machine";
466     machine->stable = 1;
467    
468     /* TODO: interrupt for PPC? */
469    
470     default_test(machine, cpu);
471     }
472    
473    
474     MACHINE_DEFAULT_CPU(bareppc)
475     {
476     machine->cpu_name = strdup("PPC970");
477     }
478    
479    
480     MACHINE_DEFAULT_CPU(testppc)
481     {
482     machine->cpu_name = strdup("PPC970");
483     }
484    
485    
486     MACHINE_REGISTER(bareppc)
487     {
488     MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
489     ARCH_PPC, MACHINE_BAREPPC, 1, 0);
490     me->aliases[0] = "bareppc";
491     machine_entry_add(me, ARCH_PPC);
492     }
493    
494    
495     MACHINE_REGISTER(testppc)
496     {
497     MR_DEFAULT(testppc, "Test-machine for PPC",
498     ARCH_PPC, MACHINE_TESTPPC, 1, 0);
499     me->aliases[0] = "testppc";
500     machine_entry_add(me, ARCH_PPC);
501     }
502    
503    
504     MACHINE_SETUP(baresh)
505     {
506     machine->machine_name = "Generic \"bare\" SH machine";
507     machine->stable = 1;
508     }
509    
510    
511     MACHINE_SETUP(testsh)
512     {
513     machine->machine_name = "SH test machine";
514     machine->stable = 1;
515    
516     /* TODO: interrupt for SH? */
517    
518     default_test(machine, cpu);
519     }
520    
521    
522     MACHINE_DEFAULT_CPU(baresh)
523     {
524     machine->cpu_name = strdup("SH");
525     }
526    
527    
528     MACHINE_DEFAULT_CPU(testsh)
529     {
530     machine->cpu_name = strdup("SH");
531     }
532    
533    
534     MACHINE_REGISTER(baresh)
535     {
536     MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
537     ARCH_SH, MACHINE_BARESH, 1, 0);
538     me->aliases[0] = "baresh";
539     machine_entry_add(me, ARCH_SH);
540     }
541    
542    
543     MACHINE_REGISTER(testsh)
544     {
545     MR_DEFAULT(testsh, "Test-machine for SH",
546     ARCH_SH, MACHINE_TESTSH, 1, 0);
547     me->aliases[0] = "testsh";
548     machine_entry_add(me, ARCH_SH);
549     }
550    
551    
552     MACHINE_SETUP(baresparc)
553     {
554     machine->machine_name = "Generic \"bare\" SPARC machine";
555     machine->stable = 1;
556     }
557    
558    
559     MACHINE_SETUP(testsparc)
560     {
561     machine->machine_name = "SPARC test machine";
562     machine->stable = 1;
563    
564     /* TODO: interrupt for SPARC? */
565    
566     default_test(machine, cpu);
567     }
568    
569    
570     MACHINE_DEFAULT_CPU(baresparc)
571     {
572 dpavlin 24 machine->cpu_name = strdup("UltraSPARC");
573 dpavlin 22 }
574    
575    
576     MACHINE_DEFAULT_CPU(testsparc)
577     {
578 dpavlin 24 machine->cpu_name = strdup("UltraSPARC");
579 dpavlin 22 }
580    
581    
582     MACHINE_REGISTER(baresparc)
583     {
584     MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
585     ARCH_SPARC, MACHINE_BARESPARC, 1, 0);
586     me->aliases[0] = "baresparc";
587     machine_entry_add(me, ARCH_SPARC);
588     }
589    
590    
591     MACHINE_REGISTER(testsparc)
592     {
593     MR_DEFAULT(testsparc, "Test-machine for SPARC",
594     ARCH_SPARC, MACHINE_TESTSPARC, 1, 0);
595     me->aliases[0] = "testsparc";
596     machine_entry_add(me, ARCH_SPARC);
597     }
598    

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