/[gxemul]/trunk/src/machines/machine_test.c
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Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 22 /*
2     * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: machine_test.c,v 1.1 2006/01/01 20:41:25 debug Exp $
29     *
30     * Various "test" machines (bare machines with just a CPU, or a bare machine
31     * plus some experimental devices).
32     */
33    
34     #include <stdio.h>
35     #include <string.h>
36    
37     #include "cpu.h"
38     #include "device.h"
39     #include "devices.h"
40     #include "machine.h"
41     #include "memory.h"
42     #include "misc.h"
43     #include "mp.h"
44    
45    
46     static void default_test(struct machine *machine, struct cpu *cpu)
47     {
48     char tmpstr[1000];
49     snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%llx irq=0",
50     (long long)DEV_CONS_ADDRESS);
51     machine->main_console_handle = (size_t)device_add(machine, tmpstr);
52    
53     snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%llx",
54     (long long)DEV_MP_ADDRESS);
55     device_add(machine, tmpstr);
56    
57     dev_fb_init(machine, machine->memory, DEV_FB_ADDRESS, VFB_GENERIC,
58     640,480, 640,480, 24, "testalpha generic");
59    
60     snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%llx",
61     (long long)DEV_DISK_ADDRESS);
62     device_add(machine, tmpstr);
63    
64     snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%llx irq=0",
65     (long long)DEV_ETHER_ADDRESS);
66     device_add(machine, tmpstr);
67     }
68    
69    
70     MACHINE_SETUP(barealpha)
71     {
72     machine->machine_name = "Generic \"bare\" Alpha machine";
73     machine->stable = 1;
74     }
75    
76    
77     MACHINE_SETUP(testalpha)
78     {
79     machine->machine_name = "Alpha test machine";
80     machine->stable = 1;
81    
82     /* TODO: interrupt for Alpha? */
83    
84     default_test(machine, cpu);
85     }
86    
87    
88     MACHINE_DEFAULT_CPU(barealpha)
89     {
90     machine->cpu_name = strdup("Alpha");
91     }
92    
93    
94     MACHINE_DEFAULT_CPU(testalpha)
95     {
96     machine->cpu_name = strdup("Alpha");
97     }
98    
99    
100     MACHINE_REGISTER(barealpha)
101     {
102     MR_DEFAULT(barealpha, "Generic \"bare\" Alpha machine",
103     ARCH_ALPHA, MACHINE_BAREALPHA, 1, 0);
104     me->aliases[0] = "barealpha";
105     machine_entry_add(me, ARCH_ALPHA);
106     }
107    
108    
109     MACHINE_REGISTER(testalpha)
110     {
111     MR_DEFAULT(testalpha, "Test-machine for Alpha",
112     ARCH_ALPHA, MACHINE_TESTALPHA, 1, 0);
113     me->aliases[0] = "testalpha";
114     machine_entry_add(me, ARCH_ALPHA);
115     }
116    
117    
118     MACHINE_SETUP(barearm)
119     {
120     machine->machine_name = "Generic \"bare\" ARM machine";
121     machine->stable = 1;
122     }
123    
124    
125     MACHINE_SETUP(testarm)
126     {
127     machine->machine_name = "ARM test machine";
128     machine->stable = 1;
129    
130     /* TODO: interrupt for ARM? */
131    
132     default_test(machine, cpu);
133    
134     /*
135     * Place a tiny stub at end of memory, and set the link register to
136     * point to it. This stub halts the machine (making it easy to try
137     * out simple stand-alone C functions).
138     */
139     cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
140     cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
141     store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
142     store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
143     store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
144     }
145    
146    
147     MACHINE_DEFAULT_CPU(barearm)
148     {
149     machine->cpu_name = strdup("SA1110");
150     }
151    
152    
153     MACHINE_DEFAULT_CPU(testarm)
154     {
155     machine->cpu_name = strdup("SA1110");
156     }
157    
158    
159     MACHINE_REGISTER(barearm)
160     {
161     MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
162     ARCH_ARM, MACHINE_BAREARM, 1, 0);
163     me->aliases[0] = "barearm";
164     machine_entry_add(me, ARCH_ARM);
165     }
166    
167    
168     MACHINE_REGISTER(testarm)
169     {
170     MR_DEFAULT(testarm, "Test-machine for ARM",
171     ARCH_ARM, MACHINE_TESTARM, 1, 0);
172     me->aliases[0] = "testarm";
173     machine_entry_add(me, ARCH_ARM);
174     }
175    
176    
177    
178     MACHINE_SETUP(bareavr)
179     {
180     machine->machine_name = "Generic \"bare\" AVR machine";
181     machine->stable = 1;
182     }
183    
184    
185     MACHINE_DEFAULT_CPU(bareavr)
186     {
187     machine->cpu_name = strdup("AVR");
188     }
189    
190    
191     MACHINE_REGISTER(bareavr)
192     {
193     MR_DEFAULT(bareavr, "Generic \"bare\" AVR machine",
194     ARCH_AVR, MACHINE_BAREAVR, 1, 0);
195     me->aliases[0] = "bareavr";
196     machine_entry_add(me, ARCH_AVR);
197     }
198    
199    
200     MACHINE_SETUP(barehppa)
201     {
202     machine->machine_name = "Generic \"bare\" HPPA machine";
203     machine->stable = 1;
204     }
205    
206    
207     MACHINE_SETUP(testhppa)
208     {
209     machine->machine_name = "HPPA test machine";
210     machine->stable = 1;
211    
212     /* TODO: interrupt for HPPA? */
213    
214     default_test(machine, cpu);
215     }
216    
217    
218     MACHINE_DEFAULT_CPU(barehppa)
219     {
220     machine->cpu_name = strdup("HPPA");
221     }
222    
223    
224     MACHINE_DEFAULT_CPU(testhppa)
225     {
226     machine->cpu_name = strdup("HPPA");
227     }
228    
229    
230     MACHINE_REGISTER(barehppa)
231     {
232     MR_DEFAULT(barehppa, "Generic \"bare\" HPPA machine",
233     ARCH_HPPA, MACHINE_BAREHPPA, 1, 0);
234     me->aliases[0] = "barehppa";
235     machine_entry_add(me, ARCH_HPPA);
236     }
237    
238    
239     MACHINE_REGISTER(testhppa)
240     {
241     MR_DEFAULT(testhppa, "Test-machine for HPPA",
242     ARCH_HPPA, MACHINE_TESTHPPA, 1, 0);
243     me->aliases[0] = "testhppa";
244     machine_entry_add(me, ARCH_HPPA);
245     }
246    
247    
248     MACHINE_SETUP(barei960)
249     {
250     machine->machine_name = "Generic \"bare\" i960 machine";
251     machine->stable = 1;
252     }
253    
254    
255     MACHINE_SETUP(testi960)
256     {
257     machine->machine_name = "i960 test machine";
258     machine->stable = 1;
259    
260     /* TODO: interrupt for i960? */
261    
262     default_test(machine, cpu);
263     }
264    
265    
266     MACHINE_DEFAULT_CPU(barei960)
267     {
268     machine->cpu_name = strdup("i960");
269     }
270    
271    
272     MACHINE_DEFAULT_CPU(testi960)
273     {
274     machine->cpu_name = strdup("i960");
275     }
276    
277    
278     MACHINE_REGISTER(barei960)
279     {
280     MR_DEFAULT(barei960, "Generic \"bare\" i960 machine",
281     ARCH_I960, MACHINE_BAREI960, 1, 0);
282     me->aliases[0] = "barei960";
283     machine_entry_add(me, ARCH_I960);
284     }
285    
286    
287     MACHINE_REGISTER(testi960)
288     {
289     MR_DEFAULT(testi960, "Test-machine for i960",
290     ARCH_I960, MACHINE_TESTI960, 1, 0);
291     me->aliases[0] = "testi960";
292     machine_entry_add(me, ARCH_I960);
293     }
294    
295    
296     MACHINE_SETUP(bareia64)
297     {
298     machine->machine_name = "Generic \"bare\" IA64 machine";
299     machine->stable = 1;
300     }
301    
302    
303     MACHINE_SETUP(testia64)
304     {
305     machine->machine_name = "IA64 test machine";
306     machine->stable = 1;
307    
308     /* TODO: interrupt for IA64? */
309    
310     default_test(machine, cpu);
311     }
312    
313    
314     MACHINE_DEFAULT_CPU(bareia64)
315     {
316     machine->cpu_name = strdup("IA64");
317     }
318    
319    
320     MACHINE_DEFAULT_CPU(testia64)
321     {
322     machine->cpu_name = strdup("IA64");
323     }
324    
325    
326     MACHINE_REGISTER(bareia64)
327     {
328     MR_DEFAULT(bareia64, "Generic \"bare\" IA64 machine",
329     ARCH_IA64, MACHINE_BAREIA64, 1, 0);
330     me->aliases[0] = "bareia64";
331     machine_entry_add(me, ARCH_IA64);
332     }
333    
334    
335     MACHINE_REGISTER(testia64)
336     {
337     MR_DEFAULT(testia64, "Test-machine for IA64",
338     ARCH_IA64, MACHINE_TESTIA64, 1, 0);
339     me->aliases[0] = "testia64";
340     machine_entry_add(me, ARCH_IA64);
341     }
342    
343    
344     MACHINE_SETUP(barem68k)
345     {
346     machine->machine_name = "Generic \"bare\" M68K machine";
347     machine->stable = 1;
348     }
349    
350    
351     MACHINE_SETUP(testm68k)
352     {
353     machine->machine_name = "M68K test machine";
354     machine->stable = 1;
355    
356     /* TODO: interrupt for M68K? */
357    
358     default_test(machine, cpu);
359     }
360    
361    
362     MACHINE_DEFAULT_CPU(barem68k)
363     {
364     machine->cpu_name = strdup("68020");
365     }
366    
367    
368     MACHINE_DEFAULT_CPU(testm68k)
369     {
370     machine->cpu_name = strdup("68020");
371     }
372    
373    
374     MACHINE_REGISTER(barem68k)
375     {
376     MR_DEFAULT(barem68k, "Generic \"bare\" M68K machine",
377     ARCH_M68K, MACHINE_BAREM68K, 1, 0);
378     me->aliases[0] = "barem68k";
379     machine_entry_add(me, ARCH_M68K);
380     }
381    
382    
383     MACHINE_REGISTER(testm68k)
384     {
385     MR_DEFAULT(testm68k, "Test-machine for M68K",
386     ARCH_M68K, MACHINE_TESTM68K, 1, 0);
387     me->aliases[0] = "testm68k";
388     machine_entry_add(me, ARCH_M68K);
389     }
390    
391    
392     MACHINE_SETUP(baremips)
393     {
394     machine->machine_name = "Generic \"bare\" MIPS machine";
395     machine->stable = 1;
396     cpu->byte_order = EMUL_BIG_ENDIAN;
397     }
398    
399    
400     MACHINE_SETUP(testmips)
401     {
402     /*
403     * A MIPS test machine (which happens to work with the
404     * code in my master's thesis). :-)
405     *
406     * IRQ map:
407     * 7 CPU counter
408     * 6 SMP IPIs
409     * 5 not used yet
410     * 4 not used yet
411     * 3 ethernet
412     * 2 serial console
413     */
414    
415     char tmpstr[1000];
416    
417     machine->machine_name = "MIPS test machine";
418     machine->stable = 1;
419     cpu->byte_order = EMUL_BIG_ENDIAN;
420    
421     snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%llx irq=2",
422     (long long)DEV_CONS_ADDRESS);
423     machine->main_console_handle = (size_t)device_add(machine, tmpstr);
424    
425     snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%llx",
426     (long long)DEV_MP_ADDRESS);
427     device_add(machine, tmpstr);
428    
429     dev_fb_init(machine, machine->memory, DEV_FB_ADDRESS, VFB_GENERIC,
430     640,480, 640,480, 24, "testmips generic");
431    
432     snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%llx",
433     (long long)DEV_DISK_ADDRESS);
434     device_add(machine, tmpstr);
435    
436     snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%llx irq=3",
437     (long long)DEV_ETHER_ADDRESS);
438     device_add(machine, tmpstr);
439     }
440    
441    
442     MACHINE_DEFAULT_CPU(baremips)
443     {
444     machine->cpu_name = strdup("R4000");
445     }
446    
447    
448     MACHINE_DEFAULT_CPU(testmips)
449     {
450     machine->cpu_name = strdup("R4000");
451     }
452    
453    
454     MACHINE_REGISTER(baremips)
455     {
456     MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
457     ARCH_MIPS, MACHINE_BAREMIPS, 1, 0);
458     me->aliases[0] = "baremips";
459     machine_entry_add(me, ARCH_MIPS);
460     }
461    
462    
463     MACHINE_REGISTER(testmips)
464     {
465     MR_DEFAULT(testmips, "Test-machine for MIPS",
466     ARCH_MIPS, MACHINE_TESTMIPS, 1, 0);
467     me->aliases[0] = "testmips";
468     machine_entry_add(me, ARCH_MIPS);
469     }
470    
471    
472     MACHINE_SETUP(bareppc)
473     {
474     machine->machine_name = "Generic \"bare\" PPC machine";
475     machine->stable = 1;
476     }
477    
478    
479     MACHINE_SETUP(testppc)
480     {
481     machine->machine_name = "PPC test machine";
482     machine->stable = 1;
483    
484     /* TODO: interrupt for PPC? */
485    
486     default_test(machine, cpu);
487     }
488    
489    
490     MACHINE_DEFAULT_CPU(bareppc)
491     {
492     machine->cpu_name = strdup("PPC970");
493     }
494    
495    
496     MACHINE_DEFAULT_CPU(testppc)
497     {
498     machine->cpu_name = strdup("PPC970");
499     }
500    
501    
502     MACHINE_REGISTER(bareppc)
503     {
504     MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
505     ARCH_PPC, MACHINE_BAREPPC, 1, 0);
506     me->aliases[0] = "bareppc";
507     machine_entry_add(me, ARCH_PPC);
508     }
509    
510    
511     MACHINE_REGISTER(testppc)
512     {
513     MR_DEFAULT(testppc, "Test-machine for PPC",
514     ARCH_PPC, MACHINE_TESTPPC, 1, 0);
515     me->aliases[0] = "testppc";
516     machine_entry_add(me, ARCH_PPC);
517     }
518    
519    
520     MACHINE_SETUP(baresh)
521     {
522     machine->machine_name = "Generic \"bare\" SH machine";
523     machine->stable = 1;
524     }
525    
526    
527     MACHINE_SETUP(testsh)
528     {
529     machine->machine_name = "SH test machine";
530     machine->stable = 1;
531    
532     /* TODO: interrupt for SH? */
533    
534     default_test(machine, cpu);
535     }
536    
537    
538     MACHINE_DEFAULT_CPU(baresh)
539     {
540     machine->cpu_name = strdup("SH");
541     }
542    
543    
544     MACHINE_DEFAULT_CPU(testsh)
545     {
546     machine->cpu_name = strdup("SH");
547     }
548    
549    
550     MACHINE_REGISTER(baresh)
551     {
552     MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
553     ARCH_SH, MACHINE_BARESH, 1, 0);
554     me->aliases[0] = "baresh";
555     machine_entry_add(me, ARCH_SH);
556     }
557    
558    
559     MACHINE_REGISTER(testsh)
560     {
561     MR_DEFAULT(testsh, "Test-machine for SH",
562     ARCH_SH, MACHINE_TESTSH, 1, 0);
563     me->aliases[0] = "testsh";
564     machine_entry_add(me, ARCH_SH);
565     }
566    
567    
568     MACHINE_SETUP(baresparc)
569     {
570     machine->machine_name = "Generic \"bare\" SPARC machine";
571     machine->stable = 1;
572     }
573    
574    
575     MACHINE_SETUP(testsparc)
576     {
577     machine->machine_name = "SPARC test machine";
578     machine->stable = 1;
579    
580     /* TODO: interrupt for SPARC? */
581    
582     default_test(machine, cpu);
583     }
584    
585    
586     MACHINE_DEFAULT_CPU(baresparc)
587     {
588     machine->cpu_name = strdup("SPARCv9");
589     }
590    
591    
592     MACHINE_DEFAULT_CPU(testsparc)
593     {
594     machine->cpu_name = strdup("SPARCv9");
595     }
596    
597    
598     MACHINE_REGISTER(baresparc)
599     {
600     MR_DEFAULT(baresparc, "Generic \"bare\" SPARC machine",
601     ARCH_SPARC, MACHINE_BARESPARC, 1, 0);
602     me->aliases[0] = "baresparc";
603     machine_entry_add(me, ARCH_SPARC);
604     }
605    
606    
607     MACHINE_REGISTER(testsparc)
608     {
609     MR_DEFAULT(testsparc, "Test-machine for SPARC",
610     ARCH_SPARC, MACHINE_TESTSPARC, 1, 0);
611     me->aliases[0] = "testsparc";
612     machine_entry_add(me, ARCH_SPARC);
613     }
614    

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