/[gxemul]/trunk/src/machines/machine_qemu.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/machines/machine_qemu.c

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Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 3563 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============
1 /*
2 * Copyright (C) 2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: machine_qemu.c,v 1.4 2006/08/12 19:31:36 debug Exp $
29 *
30 * This file contains semi-bogus machine descriptions for experimental
31 * machines, mimicing those emulated by Fabrice Bellard's QEMU.
32 *
33 * See e.g. http://fabrice.bellard.free.fr/qemu/mips-test-0.1.tar.gz
34 * (available from http://fabrice.bellard.free.fr/qemu/download.html).
35 */
36
37 #include <stdio.h>
38 #include <string.h>
39
40 #include "bus_isa.h"
41 #include "cpu.h"
42 #include "device.h"
43 #include "devices.h"
44 #include "machine.h"
45 #include "machine_interrupts.h"
46 #include "memory.h"
47 #include "misc.h"
48
49
50 MACHINE_SETUP(qemu_mips)
51 {
52 machine->machine_name = "QEMU MIPS";
53 cpu->byte_order = EMUL_BIG_ENDIAN;
54
55 /* An ISA bus, I/O ports at 0x14000000, memory at 0x10000000... */
56 bus_isa_init(machine, BUS_ISA_IDE0 | BUS_ISA_IDE1,
57 0x14000000ULL, 0x10000000ULL, 8, 24);
58
59 /* ... and an ISA interrupt controller, connected to MIPS irq 2: */
60 machine->md_interrupt = isa8_interrupt;
61 machine->isa_pic_data.native_irq = 2;
62
63 if (!machine->prom_emulation)
64 return;
65
66 /*
67 * Registers at startup do not seem to be defined in QEMU, but
68 * bootargs and memory size are placed just below 16 MB.
69 *
70 * Remember to start the emulator with options, e.g.:
71 *
72 * -o "console=ttyS0 root=/dev/ram rd_start=0x80800000
73 * rd_size=10000000 init=/bin/sh"
74 */
75
76 store_string(cpu, (int32_t)(0x80000000 + 16*1048576 - 256),
77 machine->boot_string_argument);
78 store_32bit_word(cpu, (int32_t)(0x80000000 + 16*1048576 - 260),
79 0x12345678);
80 store_32bit_word(cpu, (int32_t)(0x80000000 + 16*1048576 - 264),
81 machine->physical_ram_in_mb * 1048576);
82 }
83
84
85 MACHINE_DEFAULT_CPU(qemu_mips)
86 {
87 /* QEMU emulates a MIPS32 rev 1, so 4Kc will do just fine. */
88 machine->cpu_name = strdup("4Kc");
89 }
90
91
92 MACHINE_DEFAULT_RAM(qemu_mips)
93 {
94 machine->physical_ram_in_mb = 64;
95 }
96
97
98 MACHINE_REGISTER(qemu_mips)
99 {
100 MR_DEFAULT(qemu_mips, "QEMU MIPS", ARCH_MIPS, MACHINE_QEMU_MIPS);
101 me->set_default_ram = machine_default_ram_qemu_mips;
102 machine_entry_add_alias(me, "qemu_mips");
103 }
104
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