src/machines/machine_evbmips.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: machine_evbmips.c,v 1.30 2007/06/17 02:17:45 debug Exp $
 *
 *  COMMENT: MIPS evaluation boards (e.g. Malta)
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_isa.h"
#include "bus_pci.h"
#include "cpu.h"
#include "device.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "maltareg.h"


MACHINE_SETUP(evbmips)
{
        char tmpstr[1000], tmpstr2[1000];
        struct pci_data *pci_data;
        int i;

        /*  See http://www.netbsd.org/ports/evbmips/ for more info.  */

        switch (machine->machine_subtype) {

        case MACHINE_EVBMIPS_MALTA:
        case MACHINE_EVBMIPS_MALTA_BE:
                if (machine->emulated_hz == 0)
                        machine->emulated_hz = 33000000;
                cpu->byte_order = EMUL_LITTLE_ENDIAN;
                machine->machine_name = "MALTA (evbmips, little endian)";

                if (machine->machine_subtype == MACHINE_EVBMIPS_MALTA_BE) {
                        machine->machine_name = "MALTA (evbmips, big endian)";
                        cpu->byte_order = EMUL_BIG_ENDIAN;
                }

                /*  ISA bus at MIPS irq 2:  */
                snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
                    machine->path, machine->bootstrap_cpu);
                bus_isa_init(machine, tmpstr, 0, 0x18000000, 0x10000000);

                snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].4 "
                    "addr=0x%x name2=tty2 in_use=0", machine->path,
                    machine->bootstrap_cpu, MALTA_CBUSUART);
                device_add(machine, tmpstr);

                /*  Add a GT controller; timer interrupts at ISA irq 9:  */
                snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.isa.9",
                    machine->path, machine->bootstrap_cpu);
                snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i].2",
                    machine->path, machine->bootstrap_cpu);
                pci_data = dev_gt_init(machine, machine->memory, 0x1be00000,
                    tmpstr, tmpstr2, 120);

                if (machine->x11_md.in_use) {
                        if (strlen(machine->boot_string_argument) < 3) {
                                fatal("WARNING: remember to use  -o 'console="
                                    "tty0'  if you are emulating Linux. (Not"
                                    " needed for NetBSD.)\n");
                        }
                        bus_pci_add(machine, pci_data, machine->memory,
                            0, 8, 0, "s3_virge");
                }

                bus_pci_add(machine, pci_data, machine->memory,
                    0, 9, 0, "piix4_isa");
                bus_pci_add(machine, pci_data, machine->memory,
                    0, 9, 1, "piix4_ide");

                /*  pcn: Not yet, since it is just a bogus device, so far.  */
                /*  bus_pci_add(machine, pci_data, machine->memory,
                    0, 11, 0, "pcn");  */

                device_add(machine, "malta_lcd addr=0x1f000400");
                break;

        default:fatal("Unimplemented EVBMIPS model.\n");
                exit(1);
        }

        if (!machine->prom_emulation)
                return;


        /*  NetBSD/evbmips wants these: (at least for Malta)  */

        /*  a0 = argc  */
        cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;

        /*  a1 = argv  */
        cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
        store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
        store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
        store_32bit_word(cpu, (int32_t)0x9fc01008, 0);

        machine->bootstr = strdup(machine->boot_kernel_filename);
        machine->bootarg = strdup(machine->boot_string_argument);
        store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
        store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);

        /*  a2 = (yamon_env_var *)envp  */
        cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;

        yamon_machine_setup(machine, cpu->cd.mips.gpr[MIPS_GPR_A2]);

        /*  a3 = memsize  */
        cpu->cd.mips.gpr[MIPS_GPR_A3] = machine->physical_ram_in_mb * 1048576;
        /*  Hm. Linux ignores a3.  */

        /*  Set the Core ID. See maltareg.h for more info.  */
        store_32bit_word(cpu, (int32_t)(0x80000000 + MALTA_REVISION),
            (1 << 10) + 0x26);

        /*  Call vectors at 0x9fc005xx:  */
        for (i=0; i<0x100; i+=4)
                store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00500 + i,
                    (int64_t)(int32_t)0x9fc00800 + i);

        /*  "Magic trap" PROM instructions at 0x9fc008xx:  */
        for (i=0; i<0x100; i+=4)
                store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00800 + i,
                    0x00c0de0c);
}


MACHINE_DEFAULT_CPU(evbmips)
{
        switch (machine->machine_subtype) {

        case MACHINE_EVBMIPS_MALTA:
        case MACHINE_EVBMIPS_MALTA_BE:
                /*  5Kc = MIPS64 rev 1, 5KE = MIPS64 rev 2  */
                machine->cpu_name = strdup("5Kc");
                break;

        default:fatal("Unimplemented evbmips subtype.\n");
                exit(1);
        }
}


MACHINE_DEFAULT_RAM(evbmips)
{
        machine->physical_ram_in_mb = 128;
}


MACHINE_REGISTER(evbmips)
{
        MR_DEFAULT(evbmips, "MIPS evaluation boards (evbmips)",
            ARCH_MIPS, MACHINE_EVBMIPS);

        machine_entry_add_alias(me, "evbmips");

        machine_entry_add_subtype(me, "Malta", MACHINE_EVBMIPS_MALTA,
            "malta", NULL);

        machine_entry_add_subtype(me, "Malta (Big-Endian)",
            MACHINE_EVBMIPS_MALTA_BE, "maltabe", NULL);

        me->set_default_ram = machine_default_ram_evbmips;
}

1	dpavlin	22	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	22	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	44	* $Id: machine_evbmips.c,v 1.30 2007/06/17 02:17:45 debug Exp $
29	dpavlin	42	*
30			* COMMENT: MIPS evaluation boards (e.g. Malta)
31	dpavlin	22	*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36
37			#include "bus_isa.h"
38			#include "bus_pci.h"
39			#include "cpu.h"
40			#include "device.h"
41			#include "devices.h"
42			#include "machine.h"
43			#include "memory.h"
44			#include "misc.h"
45
46			#include "maltareg.h"
47
48
49			MACHINE_SETUP(evbmips)
50			{
51	dpavlin	34	char tmpstr[1000], tmpstr2[1000];
52	dpavlin	22	struct pci_data *pci_data;
53			int i;
54
55	dpavlin	42	/* See http://www.netbsd.org/ports/evbmips/ for more info. */
56	dpavlin	22
57			switch (machine->machine_subtype) {
58	dpavlin	44
59	dpavlin	22	case MACHINE_EVBMIPS_MALTA:
60			case MACHINE_EVBMIPS_MALTA_BE:
61	dpavlin	32	if (machine->emulated_hz == 0)
62			machine->emulated_hz = 33000000;
63	dpavlin	22	cpu->byte_order = EMUL_LITTLE_ENDIAN;
64			machine->machine_name = "MALTA (evbmips, little endian)";
65
66			if (machine->machine_subtype == MACHINE_EVBMIPS_MALTA_BE) {
67			machine->machine_name = "MALTA (evbmips, big endian)";
68			cpu->byte_order = EMUL_BIG_ENDIAN;
69			}
70
71	dpavlin	34	/* ISA bus at MIPS irq 2: */
72			snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
73			machine->path, machine->bootstrap_cpu);
74			bus_isa_init(machine, tmpstr, 0, 0x18000000, 0x10000000);
75	dpavlin	22
76	dpavlin	34	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].4 "
77			"addr=0x%x name2=tty2 in_use=0", machine->path,
78			machine->bootstrap_cpu, MALTA_CBUSUART);
79	dpavlin	22	device_add(machine, tmpstr);
80
81	dpavlin	34	/* Add a GT controller; timer interrupts at ISA irq 9: */
82			snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.isa.9",
83			machine->path, machine->bootstrap_cpu);
84			snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i].2",
85			machine->path, machine->bootstrap_cpu);
86	dpavlin	22	pci_data = dev_gt_init(machine, machine->memory, 0x1be00000,
87	dpavlin	34	tmpstr, tmpstr2, 120);
88	dpavlin	22
89	dpavlin	42	if (machine->x11_md.in_use) {
90	dpavlin	22	if (strlen(machine->boot_string_argument) < 3) {
91			fatal("WARNING: remember to use -o 'console="
92			"tty0' if you are emulating Linux. (Not"
93			" needed for NetBSD.)\n");
94			}
95			bus_pci_add(machine, pci_data, machine->memory,
96			0, 8, 0, "s3_virge");
97			}
98
99			bus_pci_add(machine, pci_data, machine->memory,
100			0, 9, 0, "piix4_isa");
101			bus_pci_add(machine, pci_data, machine->memory,
102			0, 9, 1, "piix4_ide");
103
104	dpavlin	32	/* pcn: Not yet, since it is just a bogus device, so far. */
105			/* bus_pci_add(machine, pci_data, machine->memory,
106			0, 11, 0, "pcn"); */
107	dpavlin	30
108	dpavlin	22	device_add(machine, "malta_lcd addr=0x1f000400");
109			break;
110
111			default:fatal("Unimplemented EVBMIPS model.\n");
112			exit(1);
113			}
114
115			if (!machine->prom_emulation)
116			return;
117
118
119			/* NetBSD/evbmips wants these: (at least for Malta) */
120
121			/* a0 = argc */
122			cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;
123
124			/* a1 = argv */
125			cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
126			store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
127			store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
128			store_32bit_word(cpu, (int32_t)0x9fc01008, 0);
129
130			machine->bootstr = strdup(machine->boot_kernel_filename);
131			machine->bootarg = strdup(machine->boot_string_argument);
132			store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
133			store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);
134
135			/* a2 = (yamon_env_var )envp /
136			cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;
137
138	dpavlin	32	yamon_machine_setup(machine, cpu->cd.mips.gpr[MIPS_GPR_A2]);
139	dpavlin	22
140			/* a3 = memsize */
141			cpu->cd.mips.gpr[MIPS_GPR_A3] = machine->physical_ram_in_mb * 1048576;
142			/* Hm. Linux ignores a3. */
143
144	dpavlin	44	/* Set the Core ID. See maltareg.h for more info. */
145	dpavlin	22	store_32bit_word(cpu, (int32_t)(0x80000000 + MALTA_REVISION),
146			(1 << 10) + 0x26);
147
148			/* Call vectors at 0x9fc005xx: */
149			for (i=0; i<0x100; i+=4)
150			store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00500 + i,
151			(int64_t)(int32_t)0x9fc00800 + i);
152	dpavlin	24
153			/* "Magic trap" PROM instructions at 0x9fc008xx: */
154			for (i=0; i<0x100; i+=4)
155			store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00800 + i,
156			0x00c0de0c);
157	dpavlin	22	}
158
159
160			MACHINE_DEFAULT_CPU(evbmips)
161			{
162			switch (machine->machine_subtype) {
163	dpavlin	38
164	dpavlin	22	case MACHINE_EVBMIPS_MALTA:
165			case MACHINE_EVBMIPS_MALTA_BE:
166	dpavlin	42	/* 5Kc = MIPS64 rev 1, 5KE = MIPS64 rev 2 */
167	dpavlin	22	machine->cpu_name = strdup("5Kc");
168			break;
169	dpavlin	38
170	dpavlin	22	default:fatal("Unimplemented evbmips subtype.\n");
171			exit(1);
172			}
173			}
174
175
176			MACHINE_DEFAULT_RAM(evbmips)
177			{
178	dpavlin	44	machine->physical_ram_in_mb = 128;
179	dpavlin	22	}
180
181
182			MACHINE_REGISTER(evbmips)
183			{
184	dpavlin	26	MR_DEFAULT(evbmips, "MIPS evaluation boards (evbmips)",
185			ARCH_MIPS, MACHINE_EVBMIPS);
186	dpavlin	24
187	dpavlin	26	machine_entry_add_alias(me, "evbmips");
188	dpavlin	24
189	dpavlin	26	machine_entry_add_subtype(me, "Malta", MACHINE_EVBMIPS_MALTA,
190			"malta", NULL);
191	dpavlin	24
192	dpavlin	26	machine_entry_add_subtype(me, "Malta (Big-Endian)",
193			MACHINE_EVBMIPS_MALTA_BE, "maltabe", NULL);
194	dpavlin	24
195	dpavlin	22	me->set_default_ram = machine_default_ram_evbmips;
196			}
197