/[gxemul]/trunk/src/machines/machine_algor.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/machines/machine_algor.c

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Revision 26 - (show annotations)
Mon Oct 8 16:20:10 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 4042 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1264 2006/06/25 11:08:04 debug Exp $
20060624	Replacing the error-prone machine type initialization stuff
		with something more reasonable.
		Finally removing the old "cpu_run" kludge; moving around stuff
		in machine.c and emul.c to better suit the dyntrans system.
		Various minor dyntrans cleanups (renaming translate_address to
		translate_v2p, and experimenting with template physpages).
20060625	Removing the speed hack which separated the vph entries into
		two halves (code vs data); things seem a lot more stable now.
		Minor performance hack: R2000/R3000 cache isolation now only
		clears address translations when going into isolation, not
		when going out of it.
		Fixing the MIPS interrupt problems by letting mtc0 immediately
		cause interrupts.

==============  RELEASE 0.4.0.1  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: machine_algor.c,v 1.6 2006/06/24 10:19:19 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34
35 #include "bus_isa.h"
36 #include "bus_pci.h"
37 #include "cpu.h"
38 #include "device.h"
39 #include "devices.h"
40 #include "machine.h"
41 #include "machine_interrupts.h"
42 #include "memory.h"
43 #include "misc.h"
44
45
46 MACHINE_SETUP(algor)
47 {
48 switch (machine->machine_subtype) {
49 case MACHINE_ALGOR_P4032:
50 machine->machine_name = "Algor P4032";
51 break;
52 case MACHINE_ALGOR_P5064:
53 machine->machine_name = "Algor P5064";
54 break;
55 default:fatal("Unimplemented Algor machine.\n");
56 exit(1);
57 }
58
59 machine->md_int.v3_data = dev_v3_init(machine, machine->memory);
60 machine->md_interrupt = isa8_interrupt;
61 machine->isa_pic_data.native_irq = 6;
62 /* Hm. ISA interrupts at 6, but "local" at 2! */
63
64 device_add(machine, "algor addr=0x1ff00000");
65
66 bus_isa_init(machine, BUS_ISA_FDC, 0x1d000000, 0x10000000, 8, 24);
67
68 bus_pci_add(machine, machine->md_int.v3_data->pci_data,
69 machine->memory, 0, 0, 0, "dec21143");
70
71 if (!machine->prom_emulation)
72 return;
73
74 /* NetBSD/algor wants these: */
75
76 /* a0 = argc */
77 cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;
78
79 /* a1 = argv */
80 cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
81 store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
82 store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
83 store_32bit_word(cpu, (int32_t)0x9fc01008, 0);
84
85 machine->bootstr = strdup(machine->boot_kernel_filename);
86 machine->bootarg = strdup(machine->boot_string_argument);
87 store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
88 store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);
89
90 /* a2 = (yamon_env_var *)envp */
91 cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;
92 {
93 char tmps[50];
94 store_32bit_word(cpu, (int32_t)0x9fc01800, 0x9fc01900);
95 store_32bit_word(cpu, (int32_t)0x9fc01804, 0x9fc01a00);
96 store_32bit_word(cpu, (int32_t)0x9fc01808, 0);
97
98 snprintf(tmps, sizeof(tmps), "memsize=0x%08x",
99 machine->physical_ram_in_mb * 1048576);
100 store_string(cpu, (int)0x9fc01900, tmps);
101 store_string(cpu, (int)0x9fc01a00,
102 "ethaddr=10:20:30:30:20:10");
103 }
104 }
105
106
107 MACHINE_DEFAULT_CPU(algor)
108 {
109 machine->cpu_name = strdup("RM5200");
110 }
111
112
113 MACHINE_REGISTER(algor)
114 {
115 MR_DEFAULT(algor, "Algor evaluation board", ARCH_MIPS, MACHINE_ALGOR);
116
117 machine_entry_add_alias(me, "algor");
118
119 machine_entry_add_subtype(me, "P4032", MACHINE_ALGOR_P4032,
120 "p4032", NULL);
121
122 machine_entry_add_subtype(me, "P5064", MACHINE_ALGOR_P5064,
123 "p5064", NULL);
124 }
125

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