/[gxemul]/trunk/src/machines/interrupts.c
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revision 31 by dpavlin, Mon Oct 8 16:20:40 2007 UTC revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: interrupts.c,v 1.10 2006/08/14 17:45:47 debug Exp $   *  $Id: interrupts.c,v 1.11 2006/08/17 16:49:22 debug Exp $
29   *   *
30   *  Machine-dependent interrupt glue.   *  Machine-dependent interrupt glue.
31   */   */
# Line 705  void cpc700_interrupt(struct machine *m, Line 705  void cpc700_interrupt(struct machine *m,
705    
706    
707  /*  /*
708   *  Interrupt function for Cobalt, evbmips (Malta), and Algor.   *  Interrupt function for Cobalt, evbmips (Malta), Algor, and QEMU_MIPS.
709   *   *
710   *  Most machines will not use secondary_mask1 and native_secondary_irq.   *  Most machines will not use secondary_mask1 and native_secondary_irq.
711   *  Algor, however, routes COM1 and COM2 interrupts to MIPS CPU interrupt 4   *  Algor, however, routes COM1 and COM2 interrupts to MIPS CPU interrupt 4
# Line 717  void isa8_interrupt(struct machine *m, s Line 717  void isa8_interrupt(struct machine *m, s
717  {  {
718          int mask, x;          int mask, x;
719          int old_isa_assert, new_isa_assert;          int old_isa_assert, new_isa_assert;
720            uint8_t old_irr1 = m->isa_pic_data.pic1->irr;
721          old_isa_assert = m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier;          old_isa_assert = old_irr1 & ~m->isa_pic_data.pic1->ier;
722    
723          irq_nr -= 8;          irq_nr -= 8;
724          mask = 1 << (irq_nr & 7);          mask = 1 << (irq_nr & 7);
# Line 735  void isa8_interrupt(struct machine *m, s Line 735  void isa8_interrupt(struct machine *m, s
735                          m->isa_pic_data.pic2->irr &= ~mask;                          m->isa_pic_data.pic2->irr &= ~mask;
736          }          }
737    
738            /*
739             *  If bit 0 in the IRR has been cleared, then we need to acknowledge
740             *  a 8253 timer interrupt.
741             */
742            if (old_irr1 & 1 && !(m->isa_pic_data.pic1->irr & 1) &&
743                m->isa_pic_data.pending_timer_interrupts != NULL &&
744                (*m->isa_pic_data.pending_timer_interrupts) > 0)
745                    (*m->isa_pic_data.pending_timer_interrupts) --;
746    
747          /*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */          /*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
748          /*  (TODO: don't hardcode this here)  */          /*  (TODO: don't hardcode this here)  */
749          if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)          if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)
# Line 779  void isa8_interrupt(struct machine *m, s Line 788  void isa8_interrupt(struct machine *m, s
788   */   */
789  void x86_pc_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)  void x86_pc_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
790  {  {
791            uint8_t old_irr1 = m->isa_pic_data.pic1->irr;
792          int mask = 1 << (irq_nr & 7);          int mask = 1 << (irq_nr & 7);
793    
794          if (irq_nr < 8) {          if (irq_nr < 8) {
# Line 798  void x86_pc_interrupt(struct machine *m, Line 808  void x86_pc_interrupt(struct machine *m,
808                          m->isa_pic_data.pic2->irr &= ~mask;                          m->isa_pic_data.pic2->irr &= ~mask;
809          }          }
810    
811            /*
812             *  If bit 0 in the IRR has been cleared, then we need to acknowledge
813             *  a 8253 timer interrupt.
814             */
815            if (old_irr1 & 1 && !(m->isa_pic_data.pic1->irr & 1) &&
816                m->isa_pic_data.pending_timer_interrupts != NULL &&
817                (*m->isa_pic_data.pending_timer_interrupts) > 0)
818                    (*m->isa_pic_data.pending_timer_interrupts) --;
819    
820          if (m->isa_pic_data.pic2 != NULL) {          if (m->isa_pic_data.pic2 != NULL) {
821                  /*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */                  /*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
822                  /*  (TODO: don't hardcode this here)  */                  /*  (TODO: don't hardcode this here)  */
# Line 828  void isa32_interrupt(struct machine *m, Line 847  void isa32_interrupt(struct machine *m,
847  {  {
848          uint32_t mask = 1 << (irq_nr & 31);          uint32_t mask = 1 << (irq_nr & 31);
849          int old_isa_assert, new_isa_assert;          int old_isa_assert, new_isa_assert;
850            uint8_t old_irr1 = m->isa_pic_data.pic1->irr;
851    
852          old_isa_assert = m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier;          old_isa_assert = old_irr1 & ~m->isa_pic_data.pic1->ier;
853    
854          if (irq_nr >= 32 && irq_nr < 32 + 8) {          if (irq_nr >= 32 && irq_nr < 32 + 8) {
855                  int mm = 1 << (irq_nr & 7);                  int mm = 1 << (irq_nr & 7);
# Line 845  void isa32_interrupt(struct machine *m, Line 865  void isa32_interrupt(struct machine *m,
865                          m->isa_pic_data.pic2->irr &= ~mm;                          m->isa_pic_data.pic2->irr &= ~mm;
866          }          }
867    
868            /*
869             *  If bit 0 in the IRR has been cleared, then we need to acknowledge
870             *  a 8253 timer interrupt.
871             */
872            if (old_irr1 & 1 && !(m->isa_pic_data.pic1->irr & 1) &&
873                m->isa_pic_data.pending_timer_interrupts != NULL &&
874                (*m->isa_pic_data.pending_timer_interrupts) > 0)
875                    (*m->isa_pic_data.pending_timer_interrupts) --;
876    
877          /*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */          /*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
878          /*  (TODO: don't hardcode this here)  */          /*  (TODO: don't hardcode this here)  */
879          if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)          if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)
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