/[gxemul]/trunk/src/machines/interrupts.c
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Revision 24 - (hide annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 7 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 dpavlin 22 /*
2     * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 24 * $Id: interrupts.c,v 1.9 2006/05/17 20:27:31 debug Exp $
29 dpavlin 22 *
30     * Machine-dependent interrupt glue.
31     */
32    
33     #include <stdio.h>
34     #include <string.h>
35    
36     #include "cpu.h"
37     #include "devices.h"
38     #include "machine.h"
39     #include "machine_interrupts.h"
40     #include "misc.h"
41    
42     #include "crimereg.h"
43    
44     #include "dec_kmin.h"
45     #include "dec_kn01.h"
46     #include "dec_kn02.h"
47     #include "dec_kn03.h"
48     #include "dec_5100.h"
49     #include "dec_maxine.h"
50    
51    
52     /*
53     * DECstation KN02 interrupts:
54     */
55     void kn02_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
56     {
57     int current;
58    
59     irq_nr -= 8;
60     irq_nr &= 0xff;
61    
62     if (assrt) {
63     /* OR in the irq_nr into the CSR: */
64     m->md_int.kn02_csr->csr[0] |= irq_nr;
65     } else {
66     /* AND out the irq_nr from the CSR: */
67     m->md_int.kn02_csr->csr[0] &= ~irq_nr;
68     }
69    
70     current = m->md_int.kn02_csr->csr[0] & m->md_int.kn02_csr->csr[2];
71     if (current == 0)
72     cpu_interrupt_ack(cpu, 2);
73     else
74     cpu_interrupt(cpu, 2);
75     }
76    
77    
78     /*
79     * DECstation KMIN interrupts:
80     *
81     * TC slot 3 = system slot.
82     */
83     void kmin_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
84     {
85     irq_nr -= 8;
86     /* debug("kmin_interrupt(): irq_nr=%i assrt=%i\n", irq_nr, assrt); */
87    
88     if (assrt)
89     m->md_int.dec_ioasic_data->reg[(IOASIC_INTR -
90     IOASIC_SLOT_1_START) / 0x10] |= irq_nr;
91     else
92     m->md_int.dec_ioasic_data->reg[(IOASIC_INTR -
93     IOASIC_SLOT_1_START) / 0x10] &= ~irq_nr;
94    
95     if (m->md_int.dec_ioasic_data->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
96     / 0x10] & m->md_int.dec_ioasic_data->reg[(IOASIC_IMSK -
97     IOASIC_SLOT_1_START) / 0x10])
98     cpu_interrupt(cpu, KMIN_INT_TC3);
99     else
100     cpu_interrupt_ack(cpu, KMIN_INT_TC3);
101     }
102    
103    
104     /*
105     * DECstation KN03 interrupts:
106     */
107     void kn03_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
108     {
109     irq_nr -= 8;
110     /* debug("kn03_interrupt(): irq_nr=0x%x assrt=%i\n",
111     irq_nr, assrt); */
112    
113     if (assrt)
114     m->md_int.dec_ioasic_data->reg[(IOASIC_INTR -
115     IOASIC_SLOT_1_START) / 0x10] |= irq_nr;
116     else
117     m->md_int.dec_ioasic_data->reg[(IOASIC_INTR -
118     IOASIC_SLOT_1_START) / 0x10] &= ~irq_nr;
119    
120     if (m->md_int.dec_ioasic_data->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
121     / 0x10] & m->md_int.dec_ioasic_data->reg[(IOASIC_IMSK -
122     IOASIC_SLOT_1_START) / 0x10])
123     cpu_interrupt(cpu, KN03_INT_ASIC);
124     else
125     cpu_interrupt_ack(cpu, KN03_INT_ASIC);
126     }
127    
128    
129     /*
130     * DECstation MAXINE interrupts:
131     */
132     void maxine_interrupt(struct machine *m, struct cpu *cpu,
133     int irq_nr, int assrt)
134     {
135     irq_nr -= 8;
136     debug("maxine_interrupt(): irq_nr=0x%x assrt=%i\n", irq_nr, assrt);
137    
138     if (assrt)
139     m->md_int.dec_ioasic_data->reg[(IOASIC_INTR -
140     IOASIC_SLOT_1_START) / 0x10] |= irq_nr;
141     else
142     m->md_int.dec_ioasic_data->reg[(IOASIC_INTR -
143     IOASIC_SLOT_1_START) / 0x10] &= ~irq_nr;
144    
145     if (m->md_int.dec_ioasic_data->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
146     / 0x10] & m->md_int.dec_ioasic_data->reg[(IOASIC_IMSK -
147     IOASIC_SLOT_1_START) / 0x10])
148     cpu_interrupt(cpu, XINE_INT_TC3);
149     else
150     cpu_interrupt_ack(cpu, XINE_INT_TC3);
151     }
152    
153    
154     /*
155     * DECstation KN230 interrupts:
156     */
157     void kn230_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
158     {
159     int r2 = 0;
160    
161     m->md_int.kn230_csr->csr |= irq_nr;
162    
163     switch (irq_nr) {
164     case KN230_CSR_INTR_SII:
165     case KN230_CSR_INTR_LANCE:
166     r2 = 3;
167     break;
168     case KN230_CSR_INTR_DZ0:
169     case KN230_CSR_INTR_OPT0:
170     case KN230_CSR_INTR_OPT1:
171     r2 = 2;
172     break;
173     default:
174     fatal("kn230_interrupt(): irq_nr = %i ?\n", irq_nr);
175     }
176    
177     if (assrt) {
178     /* OR in the irq_nr mask into the CSR: */
179     m->md_int.kn230_csr->csr |= irq_nr;
180    
181     /* Assert MIPS interrupt 2 or 3: */
182     cpu_interrupt(cpu, r2);
183     } else {
184     /* AND out the irq_nr mask from the CSR: */
185     m->md_int.kn230_csr->csr &= ~irq_nr;
186    
187     /* If the CSR interrupt bits are all zero,
188     clear the bit in the cause register as well. */
189     if (r2 == 2) {
190     /* irq 2: */
191     if ((m->md_int.kn230_csr->csr & (KN230_CSR_INTR_DZ0
192     | KN230_CSR_INTR_OPT0 | KN230_CSR_INTR_OPT1)) == 0)
193     cpu_interrupt_ack(cpu, r2);
194     } else {
195     /* irq 3: */
196     if ((m->md_int.kn230_csr->csr & (KN230_CSR_INTR_SII |
197     KN230_CSR_INTR_LANCE)) == 0)
198     cpu_interrupt_ack(cpu, r2);
199     }
200     }
201     }
202    
203    
204     /*
205     * Jazz interrupts (for Acer PICA-61 etc):
206     *
207     * 0..7 MIPS interrupts
208     * 8 + x, where x = 0..15 Jazz interrupts
209     * 8 + x, where x = 16..31 ISA interrupt (irq nr + 16)
210     */
211     void jazz_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
212     {
213     uint32_t irq;
214     int isa = 0;
215    
216     irq_nr -= 8;
217    
218     /* debug("jazz_interrupt() irq_nr = %i, assrt = %i\n",
219     irq_nr, assrt); */
220    
221     if (irq_nr >= 16) {
222     isa = 1;
223     irq_nr -= 16;
224     }
225    
226     irq = 1 << irq_nr;
227    
228     if (isa) {
229     if (assrt)
230     m->md_int.jazz_data->isa_int_asserted |= irq;
231     else
232     m->md_int.jazz_data->isa_int_asserted &= ~irq;
233     } else {
234     if (assrt)
235     m->md_int.jazz_data->int_asserted |= irq;
236     else
237     m->md_int.jazz_data->int_asserted &= ~irq;
238     }
239    
240     /* debug(" %08x %08x\n", m->md_int.jazz_data->int_asserted,
241     m->md_int.jazz_data->int_enable_mask); */
242     /* debug(" %08x %08x\n", m->md_int.jazz_data->isa_int_asserted,
243     m->md_int.jazz_data->isa_int_enable_mask); */
244    
245     if (m->md_int.jazz_data->int_asserted
246     /* & m->md_int.jazz_data->int_enable_mask */ & ~0x8000 )
247     cpu_interrupt(cpu, 3);
248     else
249     cpu_interrupt_ack(cpu, 3);
250    
251     if (m->md_int.jazz_data->isa_int_asserted &
252     m->md_int.jazz_data->isa_int_enable_mask)
253     cpu_interrupt(cpu, 4);
254     else
255     cpu_interrupt_ack(cpu, 4);
256    
257     /* TODO: this "15" (0x8000) is the timer... fix this? */
258     if (m->md_int.jazz_data->int_asserted & 0x8000)
259     cpu_interrupt(cpu, 6);
260     else
261     cpu_interrupt_ack(cpu, 6);
262     }
263    
264    
265     /*
266     * VR41xx interrupt routine:
267     *
268     * irq_nr = 8 + x
269     * x = 0..15 for level1
270     * x = 16..31 for level2
271     * x = 32+y for GIU interrupt y
272     */
273     void vr41xx_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
274     {
275     int giu_irq = 0;
276    
277     irq_nr -= 8;
278     if (irq_nr >= 32) {
279     giu_irq = irq_nr - 32;
280    
281     if (assrt)
282     m->md_int.vr41xx_data->giuint |= (1 << giu_irq);
283     else
284     m->md_int.vr41xx_data->giuint &= ~(1 << giu_irq);
285     }
286    
287     /* TODO: This is wrong. What about GIU bit 8? */
288    
289     if (irq_nr != 8) {
290     /* If any GIU bit is asserted, then assert the main
291     GIU interrupt: */
292     if (m->md_int.vr41xx_data->giuint &
293     m->md_int.vr41xx_data->giumask)
294     vr41xx_interrupt(m, cpu, 8 + 8, 1);
295     else
296     vr41xx_interrupt(m, cpu, 8 + 8, 0);
297     }
298    
299     /* debug("vr41xx_interrupt(): irq_nr=%i assrt=%i\n",
300     irq_nr, assrt); */
301    
302     if (irq_nr < 16) {
303     if (assrt)
304     m->md_int.vr41xx_data->sysint1 |= (1 << irq_nr);
305     else
306     m->md_int.vr41xx_data->sysint1 &= ~(1 << irq_nr);
307     } else if (irq_nr < 32) {
308     irq_nr -= 16;
309     if (assrt)
310     m->md_int.vr41xx_data->sysint2 |= (1 << irq_nr);
311     else
312     m->md_int.vr41xx_data->sysint2 &= ~(1 << irq_nr);
313     }
314    
315     /* TODO: Which hardware interrupt pin? */
316    
317     /* debug(" sysint1=%04x mask=%04x, sysint2=%04x mask=%04x\n",
318     m->md_int.vr41xx_data->sysint1, m->md_int.vr41xx_data->msysint1,
319     m->md_int.vr41xx_data->sysint2, m->md_int.vr41xx_data->msysint2); */
320    
321     if ((m->md_int.vr41xx_data->sysint1 & m->md_int.vr41xx_data->msysint1) |
322     (m->md_int.vr41xx_data->sysint2 & m->md_int.vr41xx_data->msysint2))
323     cpu_interrupt(cpu, 2);
324     else
325     cpu_interrupt_ack(cpu, 2);
326     }
327    
328    
329     /*
330     * Playstation 2 interrupt routine:
331     *
332     * irq_nr = 8 + x normal irq x
333     * 8 + 16 + y dma irq y
334     * 8 + 32 + 0 sbus irq 0 (pcmcia)
335     * 8 + 32 + 1 sbus irq 1 (usb)
336     */
337     void ps2_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
338     {
339     irq_nr -= 8;
340 dpavlin 24 /* debug("ps2_interrupt(): irq_nr=0x%x assrt=%i\n", irq_nr, assrt); */
341 dpavlin 22
342     if (irq_nr >= 32) {
343     int msk = 0;
344     switch (irq_nr - 32) {
345     case 0: /* PCMCIA: */
346     msk = 0x100;
347     break;
348     case 1: /* USB: */
349     msk = 0x400;
350     break;
351     default:
352     fatal("ps2_interrupt(): bad irq_nr %i\n", irq_nr);
353     }
354    
355     if (assrt)
356     m->md_int.ps2_data->sbus_smflg |= msk;
357     else
358     m->md_int.ps2_data->sbus_smflg &= ~msk;
359    
360     if (m->md_int.ps2_data->sbus_smflg != 0)
361     cpu_interrupt(cpu, 8 + 1);
362     else
363     cpu_interrupt_ack(cpu, 8 + 1);
364     return;
365     }
366    
367     if (assrt) {
368     /* OR into the INTR: */
369     if (irq_nr < 16)
370     m->md_int.ps2_data->intr |= (1 << irq_nr);
371     else
372     m->md_int.ps2_data->dmac_reg[0x601] |=
373     (1 << (irq_nr-16));
374     } else {
375     /* AND out of the INTR: */
376     if (irq_nr < 16)
377     m->md_int.ps2_data->intr &= ~(1 << irq_nr);
378     else
379     m->md_int.ps2_data->dmac_reg[0x601] &=
380     ~(1 << (irq_nr-16));
381     }
382    
383     /* TODO: Hm? How about the mask? */
384     if (m->md_int.ps2_data->intr /* & m->md_int.ps2_data->imask */ )
385     cpu_interrupt(cpu, 2);
386     else
387     cpu_interrupt_ack(cpu, 2);
388    
389     /* TODO: mask? */
390     if (m->md_int.ps2_data->dmac_reg[0x601] & 0xffff)
391     cpu_interrupt(cpu, 3);
392     else
393     cpu_interrupt_ack(cpu, 3);
394     }
395    
396    
397     /*
398     * SGI "IP22" interrupt routine:
399     */
400     void sgi_ip22_interrupt(struct machine *m, struct cpu *cpu,
401     int irq_nr, int assrt)
402     {
403     /*
404     * SGI-IP22 specific interrupt stuff:
405     *
406     * irq_nr should be 8 + x, where x = 0..31 for local0,
407     * and 32..63 for local1 interrupts.
408     * Add 64*y for "mappable" interrupts, where 1<<y is
409     * the mappable interrupt bitmask. TODO: this misses 64*0 !
410     */
411    
412     uint32_t newmask;
413     uint32_t stat, mask;
414    
415     irq_nr -= 8;
416     newmask = 1 << (irq_nr & 31);
417    
418     if (irq_nr >= 64) {
419     int ms = irq_nr / 64;
420     uint32_t new = 1 << ms;
421     if (assrt)
422     m->md_int.sgi_ip22_data->reg[4] |= new;
423     else
424     m->md_int.sgi_ip22_data->reg[4] &= ~new;
425     /* TODO: is this enough? */
426     irq_nr &= 63;
427     }
428    
429     if (irq_nr < 32) {
430     if (assrt)
431     m->md_int.sgi_ip22_data->reg[0] |= newmask;
432     else
433     m->md_int.sgi_ip22_data->reg[0] &= ~newmask;
434     } else {
435     if (assrt)
436     m->md_int.sgi_ip22_data->reg[2] |= newmask;
437     else
438     m->md_int.sgi_ip22_data->reg[2] &= ~newmask;
439     }
440    
441     /* Read stat and mask for local0: */
442     stat = m->md_int.sgi_ip22_data->reg[0];
443     mask = m->md_int.sgi_ip22_data->reg[1];
444     if ((stat & mask) == 0)
445     cpu_interrupt_ack(cpu, 2);
446     else
447     cpu_interrupt(cpu, 2);
448    
449     /* Read stat and mask for local1: */
450     stat = m->md_int.sgi_ip22_data->reg[2];
451     mask = m->md_int.sgi_ip22_data->reg[3];
452     if ((stat & mask) == 0)
453     cpu_interrupt_ack(cpu, 3);
454     else
455     cpu_interrupt(cpu, 3);
456     }
457    
458    
459     /*
460     * SGI "IP30" interrupt routine:
461     *
462     * irq_nr = 8 + 1 + nr, where nr is:
463     * 0..49 HEART irqs hardware irq 2,3,4
464     * 50 HEART timer hardware irq 5
465     * 51..63 HEART errors hardware irq 6
466     *
467     * according to Linux/IP30.
468     */
469     void sgi_ip30_interrupt(struct machine *m, struct cpu *cpu,
470     int irq_nr, int assrt)
471     {
472     uint64_t newmask;
473     uint64_t stat, mask;
474    
475     irq_nr -= 8;
476     if (irq_nr == 0)
477     goto just_assert_and_such;
478     irq_nr --;
479    
480     newmask = (int64_t)1 << irq_nr;
481    
482     if (assrt)
483     m->md_int.sgi_ip30_data->isr |= newmask;
484     else
485     m->md_int.sgi_ip30_data->isr &= ~newmask;
486    
487     just_assert_and_such:
488    
489     cpu_interrupt_ack(cpu, 2);
490     cpu_interrupt_ack(cpu, 3);
491     cpu_interrupt_ack(cpu, 4);
492     cpu_interrupt_ack(cpu, 5);
493     cpu_interrupt_ack(cpu, 6);
494    
495     stat = m->md_int.sgi_ip30_data->isr;
496     mask = m->md_int.sgi_ip30_data->imask0;
497    
498     if ((stat & mask) & 0x000000000000ffffULL)
499     cpu_interrupt(cpu, 2);
500     if ((stat & mask) & 0x00000000ffff0000ULL)
501     cpu_interrupt(cpu, 3);
502     if ((stat & mask) & 0x0003ffff00000000ULL)
503     cpu_interrupt(cpu, 4);
504     if ((stat & mask) & 0x0004000000000000ULL)
505     cpu_interrupt(cpu, 5);
506     if ((stat & mask) & 0xfff8000000000000ULL)
507     cpu_interrupt(cpu, 6);
508     }
509    
510    
511     /*
512     * SGI "IP32" interrupt routine:
513     */
514     void sgi_ip32_interrupt(struct machine *m, struct cpu *cpu,
515     int irq_nr, int assrt)
516     {
517     /*
518     * The 64-bit word at crime offset 0x10 is CRIME_INTSTAT,
519     * which contains the current interrupt bits. CRIME_INTMASK
520     * contains a mask of which bits are actually in use.
521     *
522     * crime hardcoded at 0x14000000, for SGI-IP32.
523     * If any of these bits are asserted, then physical MIPS
524     * interrupt 2 should be asserted.
525     *
526     * TODO: how should all this be done nicely?
527     */
528    
529     uint64_t crime_addr = CRIME_INTSTAT;
530     uint64_t mace_addr = 0x10;
531     uint64_t crime_interrupts, crime_interrupts_mask;
532     uint64_t mace_interrupts, mace_interrupt_mask;
533     unsigned int i;
534     unsigned char x[8];
535    
536     /* Read current MACE interrupt assertions: */
537     memcpy(x, m->md_int.ip32.mace_data->reg + mace_addr,
538     sizeof(uint64_t));
539     mace_interrupts = 0;
540     for (i=0; i<sizeof(uint64_t); i++) {
541     mace_interrupts <<= 8;
542     mace_interrupts |= x[i];
543     }
544    
545     /* Read current MACE interrupt mask: */
546     memcpy(x, m->md_int.ip32.mace_data->reg + mace_addr + 8,
547     sizeof(uint64_t));
548     mace_interrupt_mask = 0;
549     for (i=0; i<sizeof(uint64_t); i++) {
550     mace_interrupt_mask <<= 8;
551     mace_interrupt_mask |= x[i];
552     }
553    
554     /*
555     * This mapping of both MACE and CRIME interrupts into the same
556     * 'int' is really ugly.
557     *
558     * If MACE_PERIPH_MISC or MACE_PERIPH_SERIAL is set, then mask
559     * that bit out and treat the rest of the word as the mace interrupt
560     * bitmask.
561     *
562     * TODO: fix.
563     */
564     if (irq_nr & MACE_PERIPH_SERIAL) {
565     if (assrt)
566     mace_interrupts |= (irq_nr & ~MACE_PERIPH_SERIAL);
567     else
568     mace_interrupts &= ~(irq_nr & ~MACE_PERIPH_SERIAL);
569    
570     irq_nr = MACE_PERIPH_SERIAL;
571     if ((mace_interrupts & mace_interrupt_mask) == 0)
572     assrt = 0;
573     else
574     assrt = 1;
575     }
576    
577     /* Hopefully _MISC and _SERIAL will not be both on at the same time. */
578     if (irq_nr & MACE_PERIPH_MISC) {
579     if (assrt)
580     mace_interrupts |= (irq_nr & ~MACE_PERIPH_MISC);
581     else
582     mace_interrupts &= ~(irq_nr & ~MACE_PERIPH_MISC);
583    
584     irq_nr = MACE_PERIPH_MISC;
585     if ((mace_interrupts & mace_interrupt_mask) == 0)
586     assrt = 0;
587     else
588     assrt = 1;
589     }
590    
591     /* Write back MACE interrupt assertions: */
592     for (i=0; i<sizeof(uint64_t); i++)
593     x[7-i] = mace_interrupts >> (i*8);
594     memcpy(m->md_int.ip32.mace_data->reg + mace_addr, x, sizeof(uint64_t));
595    
596     /* Read CRIME_INTSTAT: */
597     memcpy(x, m->md_int.ip32.crime_data->reg + crime_addr,
598     sizeof(uint64_t));
599     crime_interrupts = 0;
600     for (i=0; i<sizeof(uint64_t); i++) {
601     crime_interrupts <<= 8;
602     crime_interrupts |= x[i];
603     }
604    
605     if (assrt)
606     crime_interrupts |= irq_nr;
607     else
608     crime_interrupts &= ~irq_nr;
609    
610     /* Write back CRIME_INTSTAT: */
611     for (i=0; i<sizeof(uint64_t); i++)
612     x[7-i] = crime_interrupts >> (i*8);
613     memcpy(m->md_int.ip32.crime_data->reg + crime_addr, x,
614     sizeof(uint64_t));
615    
616     /* Read CRIME_INTMASK: */
617     memcpy(x, m->md_int.ip32.crime_data->reg + CRIME_INTMASK,
618     sizeof(uint64_t));
619     crime_interrupts_mask = 0;
620     for (i=0; i<sizeof(uint64_t); i++) {
621     crime_interrupts_mask <<= 8;
622     crime_interrupts_mask |= x[i];
623     }
624    
625     if ((crime_interrupts & crime_interrupts_mask) == 0)
626     cpu_interrupt_ack(cpu, 2);
627     else
628     cpu_interrupt(cpu, 2);
629    
630     /* printf("sgi_crime_machine_irq(%i,%i): new interrupts = 0x%08x\n",
631     assrt, irq_nr, crime_interrupts); */
632     }
633    
634    
635     /*
636     * Au1x00 interrupt routine:
637     *
638     * TODO: This is just bogus so far. For more info, read this:
639     * http://www.meshcube.org/cgi-bin/viewcvs.cgi/kernel/linux/arch/
640     * mips/au1000/common/
641     *
642     * CPU int 2 = IC 0, request 0
643     * CPU int 3 = IC 0, request 1
644     * CPU int 4 = IC 1, request 0
645     * CPU int 5 = IC 1, request 1
646     *
647     * Interrupts 0..31 are on interrupt controller 0, interrupts 32..63 are
648     * on controller 1.
649     *
650     * Special case: if irq_nr == 64+8, then this just updates the CPU
651     * interrupt assertions.
652     */
653     void au1x00_interrupt(struct machine *m, struct cpu *cpu,
654     int irq_nr, int assrt)
655     {
656     uint32_t ms;
657    
658     irq_nr -= 8;
659     debug("au1x00_interrupt(): irq_nr=%i assrt=%i\n", irq_nr, assrt);
660    
661     if (irq_nr < 64) {
662     ms = 1 << (irq_nr & 31);
663    
664     if (assrt)
665     m->md_int.au1x00_ic_data->request0_int |= ms;
666     else
667     m->md_int.au1x00_ic_data->request0_int &= ~ms;
668    
669     /* TODO: Controller 1 */
670     }
671    
672     if ((m->md_int.au1x00_ic_data->request0_int &
673     m->md_int.au1x00_ic_data->mask) != 0)
674     cpu_interrupt(cpu, 2);
675     else
676     cpu_interrupt_ack(cpu, 2);
677    
678     /* TODO: What _is_ request1? */
679    
680     /* TODO: Controller 1 */
681     }
682    
683    
684     /*
685     * CPC700 interrupt routine:
686     *
687     * irq_nr should be 0..31. (32 means reassertion.)
688     */
689     void cpc700_interrupt(struct machine *m, struct cpu *cpu,
690     int irq_nr, int assrt)
691     {
692     if (irq_nr < 32) {
693     uint32_t mask = 1 << (irq_nr & 31);
694     if (assrt)
695     m->md_int.cpc700_data->sr |= mask;
696     else
697     m->md_int.cpc700_data->sr &= ~mask;
698     }
699    
700     if ((m->md_int.cpc700_data->sr & m->md_int.cpc700_data->er) != 0)
701     cpu_interrupt(cpu, 65);
702     else
703     cpu_interrupt_ack(cpu, 65);
704     }
705    
706    
707     /*
708     * Interrupt function for Cobalt, evbmips (Malta), and Algor.
709     *
710     * (irq_nr = 8 + 16 can be used to just reassert/deassert interrupts.)
711     */
712     void isa8_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
713     {
714     int mask, x;
715     int old_isa_assert, new_isa_assert;
716    
717     old_isa_assert = m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier;
718    
719     irq_nr -= 8;
720     mask = 1 << (irq_nr & 7);
721    
722     if (irq_nr < 8) {
723     if (assrt)
724     m->isa_pic_data.pic1->irr |= mask;
725     else
726     m->isa_pic_data.pic1->irr &= ~mask;
727     } else if (irq_nr < 16) {
728     if (assrt)
729     m->isa_pic_data.pic2->irr |= mask;
730     else
731     m->isa_pic_data.pic2->irr &= ~mask;
732     }
733    
734     /* Any interrupt assertions on PIC2 go to irq 2 on PIC1 */
735     /* (TODO: don't hardcode this here) */
736     if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)
737     m->isa_pic_data.pic1->irr |= 0x04;
738     else
739     m->isa_pic_data.pic1->irr &= ~0x04;
740    
741     /* Now, PIC1: */
742     new_isa_assert = m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier;
743     if (old_isa_assert != new_isa_assert) {
744     for (x=0; x<16; x++) {
745     if (x == 2)
746     continue;
747     if (x < 8 && (m->isa_pic_data.pic1->irr &
748     ~m->isa_pic_data.pic1->ier & (1 << x)))
749     break;
750     if (x >= 8 && (m->isa_pic_data.pic2->irr &
751     ~m->isa_pic_data.pic2->ier & (1 << (x&7))))
752     break;
753     }
754     m->isa_pic_data.last_int = x;
755     }
756    
757     if (m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier)
758     cpu_interrupt(cpu, m->isa_pic_data.native_irq);
759     else
760     cpu_interrupt_ack(cpu, m->isa_pic_data.native_irq);
761     }
762    
763    
764     /*
765     * x86 (PC) interrupts:
766     *
767     * (irq_nr = 16 can be used to just reassert/deassert interrupts.)
768     */
769     void x86_pc_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
770     {
771     int mask = 1 << (irq_nr & 7);
772    
773     if (irq_nr < 8) {
774     if (assrt)
775     m->isa_pic_data.pic1->irr |= mask;
776     else
777     m->isa_pic_data.pic1->irr &= ~mask;
778     } else if (irq_nr < 16) {
779     if (m->isa_pic_data.pic2 == NULL) {
780     fatal("x86_pc_interrupt(): pic2 used (irq_nr = %i), "
781     "but we are emulating an XT?\n", irq_nr);
782     return;
783     }
784     if (assrt)
785     m->isa_pic_data.pic2->irr |= mask;
786     else
787     m->isa_pic_data.pic2->irr &= ~mask;
788     }
789    
790     if (m->isa_pic_data.pic2 != NULL) {
791     /* Any interrupt assertions on PIC2 go to irq 2 on PIC1 */
792     /* (TODO: don't hardcode this here) */
793     if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)
794     m->isa_pic_data.pic1->irr |= 0x04;
795     else
796     m->isa_pic_data.pic1->irr &= ~0x04;
797     }
798    
799     /* Now, PIC1: */
800     if (m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier)
801     cpu->cd.x86.interrupt_asserted = 1;
802     else
803     cpu->cd.x86.interrupt_asserted = 0;
804     }
805    
806    
807     /*
808     * "Generic" ISA interrupt management, 32 native interrupts, 16 ISA
809     * interrupts. So far: Footbridge (CATS, NetWinder), BeBox, and PReP.
810     *
811     * 0..31 = footbridge interrupt
812     * 32..47 = ISA interrupts
813     * 48 = ISA reassert
814     * 64 = reassert (non-ISA)
815     */
816     void isa32_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
817     {
818     uint32_t mask = 1 << (irq_nr & 31);
819     int old_isa_assert, new_isa_assert;
820    
821     old_isa_assert = m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier;
822    
823     if (irq_nr >= 32 && irq_nr < 32 + 8) {
824     int mm = 1 << (irq_nr & 7);
825     if (assrt)
826     m->isa_pic_data.pic1->irr |= mm;
827     else
828     m->isa_pic_data.pic1->irr &= ~mm;
829     } else if (irq_nr >= 32+8 && irq_nr < 32+16) {
830     int mm = 1 << (irq_nr & 7);
831     if (assrt)
832     m->isa_pic_data.pic2->irr |= mm;
833     else
834     m->isa_pic_data.pic2->irr &= ~mm;
835     }
836    
837     /* Any interrupt assertions on PIC2 go to irq 2 on PIC1 */
838     /* (TODO: don't hardcode this here) */
839     if (m->isa_pic_data.pic2->irr & ~m->isa_pic_data.pic2->ier)
840     m->isa_pic_data.pic1->irr |= 0x04;
841     else
842     m->isa_pic_data.pic1->irr &= ~0x04;
843    
844     /* Now, PIC1: */
845     new_isa_assert = m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier;
846     if (old_isa_assert != new_isa_assert || irq_nr == 48) {
847     if (new_isa_assert) {
848     int x;
849     for (x=0; x<16; x++) {
850     if (x == 2)
851     continue;
852     if (x < 8 && (m->isa_pic_data.pic1->irr &
853     ~m->isa_pic_data.pic1->ier & (1 << x)))
854     break;
855     if (x >= 8 && (m->isa_pic_data.pic2->irr &
856     ~m->isa_pic_data.pic2->ier & (1 << (x&7))))
857     break;
858     }
859     m->isa_pic_data.last_int = x;
860     cpu_interrupt(cpu, m->isa_pic_data.native_irq);
861     } else
862     cpu_interrupt_ack(cpu, m->isa_pic_data.native_irq);
863     return;
864     }
865    
866     switch (m->machine_type) {
867     case MACHINE_CATS:
868     case MACHINE_NETWINDER:
869     if (irq_nr < 32) {
870     if (assrt)
871     m->md_int.footbridge_data->irq_status |= mask;
872     else
873     m->md_int.footbridge_data->irq_status &= ~mask;
874     }
875     if (m->md_int.footbridge_data->irq_status &
876     m->md_int.footbridge_data->irq_enable)
877     cpu_interrupt(cpu, 65);
878     else
879     cpu_interrupt_ack(cpu, 65);
880     break;
881     case MACHINE_BEBOX:
882     if (irq_nr < 32) {
883     if (assrt)
884     m->md_int.bebox_data->int_status |= mask;
885     else
886     m->md_int.bebox_data->int_status &= ~mask;
887     }
888     if (m->md_int.bebox_data->int_status &
889     m->md_int.bebox_data->cpu0_int_mask)
890     cpu_interrupt(m->cpus[0], 65);
891     else
892     cpu_interrupt_ack(m->cpus[0], 65);
893     if (m->ncpus > 1 &&
894     m->md_int.bebox_data->int_status &
895     m->md_int.bebox_data->cpu1_int_mask)
896     cpu_interrupt(m->cpus[1], 65);
897     else
898     cpu_interrupt_ack(m->cpus[1], 65);
899     break;
900     case MACHINE_PREP:
901     case MACHINE_MVMEPPC:
902     if (irq_nr < 32) {
903     if (assrt)
904     m->md_int.prep_data->int_status |= mask;
905     else
906     m->md_int.prep_data->int_status &= ~mask;
907     }
908     if (m->md_int.prep_data->int_status & 2)
909     cpu_interrupt(cpu, 65);
910     else
911     cpu_interrupt_ack(cpu, 65);
912     break;
913     }
914     }
915    
916    
917     /*
918     * Grand Central interrupt handler.
919     *
920     * (Used by MacPPC.)
921     */
922     void gc_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
923     {
924     uint32_t mask = 1 << (irq_nr & 31);
925     if (irq_nr < 32) {
926     if (assrt)
927     m->md_int.gc_data->status_lo |= mask;
928     else
929     m->md_int.gc_data->status_lo &= ~mask;
930     }
931     if (irq_nr >= 32 && irq_nr < 64) {
932     if (assrt)
933     m->md_int.gc_data->status_hi |= mask;
934     else
935     m->md_int.gc_data->status_hi &= ~mask;
936     }
937    
938 dpavlin 24 #if 0
939 dpavlin 22 printf("status = %08x %08x enable = %08x %08x\n",
940     m->md_int.gc_data->status_hi, m->md_int.gc_data->status_lo,
941     m->md_int.gc_data->enable_hi, m->md_int.gc_data->enable_lo);
942     #endif
943    
944     if (m->md_int.gc_data->status_lo & m->md_int.gc_data->enable_lo ||
945     m->md_int.gc_data->status_hi & m->md_int.gc_data->enable_hi)
946     cpu_interrupt(m->cpus[0], 65);
947     else
948     cpu_interrupt_ack(m->cpus[0], 65);
949     }
950    
951    
952     /*
953     * i80321 (ARM) Interrupt Controller.
954     *
955     * (Used by the IQ80321 machine.)
956     */
957     void i80321_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt)
958     {
959     uint32_t mask = 1 << (irq_nr & 31);
960     if (irq_nr < 32) {
961     if (assrt)
962     cpu->cd.arm.i80321_isrc |= mask;
963     else
964     cpu->cd.arm.i80321_isrc &= ~mask;
965     }
966    
967 dpavlin 24 /* fatal("isrc = %08x inten = %08x\n",
968 dpavlin 22 cpu->cd.arm.i80321_isrc, cpu->cd.arm.i80321_inten); */
969    
970     if (cpu->cd.arm.i80321_isrc & cpu->cd.arm.i80321_inten)
971     cpu_interrupt(m->cpus[0], 65);
972     else
973     cpu_interrupt_ack(m->cpus[0], 65);
974     }
975    

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