/[gxemul]/trunk/src/include/z8530reg.h
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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 5 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /* GXemul: $Id: z8530reg.h,v 1.1 2005/12/02 01:46:31 debug Exp $ */
2 /* $NetBSD: z8530reg.h,v 1.11 2003/11/02 11:07:46 wiz Exp $ */
3
4 #ifndef Z8530REG_H
5 #define Z8530REG_H
6
7 /*
8 * Copyright (c) 1992, 1993
9 * The Regents of the University of California. All rights reserved.
10 *
11 * This software was developed by the Computer Systems Engineering group
12 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
13 * contributed to Berkeley.
14 *
15 * All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Lawrence Berkeley Laboratory.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 * 1. Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * 3. Neither the name of the University nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 * SUCH DAMAGE.
43 *
44 * @(#)zsreg.h 8.1 (Berkeley) 6/11/93
45 */
46
47 /*
48 * Zilog SCC registers, as implemented on the Sun-4c.
49 *
50 * Each Z8530 implements two channels (called `a' and `b').
51 *
52 * The damnable chip was designed to fit on Z80 I/O ports, and thus
53 * has everything multiplexed out the wazoo. We have to select
54 * a register, then read or write the register, and so on. Worse,
55 * the parameter bits are scattered all over the register space.
56 * This thing is full of `miscellaneous' control registers.
57 *
58 * Worse yet, the registers have incompatible functions on read
59 * and write operations. We describe the registers below according
60 * to whether they are `read registers' (RR) or `write registers' (WR).
61 * As if this were not enough, some of the channel B status bits show
62 * up in channel A, and vice versa. The blasted thing shares write
63 * registers 2 and 9 across both channels, and reads registers 2 and 3
64 * differently for the two channels. We can, however, ignore this much
65 * of the time.
66 *
67 * This file also includes flags for the Z85C30 and Z85230 enhanced scc.
68 * The CMOS 8530 includes extra SDLC functionality, and is used in a
69 * number of Macs (often in the Z85C80, an 85C30 combined w/ a SCSI
70 * controller). -wrs
71 *
72 * Some of the names in this files were chosen to make the hsis driver
73 * work unchanged (which means that they will match some in SunOS).
74 *
75 * `S.C.' stands for Special Condition, which is any of these:
76 * receiver overrun (aka silo overflow)
77 * framing error (missing stop bit, etc)
78 * end of frame (in synchronous modes)
79 * parity error (when `parity error is S.C.' is set)
80 *
81 * Registers with only a single `numeric value' get a name.
82 * Other registers hold bits and are only numbered; the bit
83 * definitions imply the register number (see below).
84 *
85 * We never use the receive and transmit data registers as
86 * indirects (choosing instead the zc_data register), so they
87 * are not defined here.
88 */
89 #define ZSRR_IVEC 2 /* interrupt vector (channel 0) */
90 #define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */
91 #define ZSRR_TXSYNC 6 /* sync transmit char (monosync mode) */
92 #define ZSRR_RXSYNC 7 /* sync receive char (monosync mode) */
93 #define ZSRR_SYNCLO 6 /* sync low byte (bisync mode) */
94 #define ZSRR_SYNCHI 7 /* sync high byte (bisync mode) */
95 #define ZSRR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */
96 #define ZSRR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */
97 #define ZSRR_BAUDLO 12 /* baud rate generator (low half) */
98 #define ZSRR_BAUDHI 13 /* baud rate generator (high half) */
99 #define ZSRR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/
100
101 #define ZSWR_IVEC 2 /* interrupt vector (shared) */
102 #define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */
103 #define ZSWR_RXSYNC 7 /* sync receive char (monosync mode) */
104 #define ZSWR_SYNCLO 6 /* sync low byte (bisync mode) */
105 #define ZSWR_SYNCHI 7 /* sync high byte (bisync mode) */
106 #define ZSWR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */
107 #define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */
108 #define ZSWR_BAUDLO 12 /* baud rate generator (low half) */
109 #define ZSWR_BAUDHI 13 /* baud rate generator (high half) */
110 #define ZSWR_ENHANCED 7 /* write address of WR7' */
111
112 /*
113 * Registers 0 through 7 may be written with any one of the 8 command
114 * modifiers, and/or any one of the 4 reset modifiers, defined below.
115 * To write registers 8 through 15, however, the command modifier must
116 * always be `point high'. Rather than track this bizzareness all over
117 * the driver, we try to avoid using any modifiers, ever (but they are
118 * defined here if you want them).
119 */
120 #define ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */
121 #define ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */
122 #define ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */
123 #define ZSM_NULL 0x00 /* nothing special */
124
125 #define ZSM_RESET_IUS 0x38 /* reset interrupt under service */
126 #define ZSM_RESET_ERR 0x30 /* reset error cond */
127 #define ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */
128 #define ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */
129 #define ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */
130 #define ZSM_RESET_STINT 0x10 /* reset external/status interrupt */
131 #define ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */
132 #define ZSM_NULL 0x00 /* nothing special */
133
134 /*
135 * Commands for Write Register 0 (`Command Register').
136 * These are just the command modifiers or'ed with register number 0
137 * (which of course equals the command modifier).
138 */
139 #define ZSWR0_RESET_EOM ZSM_RESET_TXUEOM
140 #define ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC
141 #define ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC
142 #define ZSWR0_CLR_INTR ZSM_RESET_IUS
143 #define ZSWR0_RESET_ERRORS ZSM_RESET_ERR
144 #define ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC
145 #define ZSWR0_SEND_ABORT ZSM_SEND_ABORT
146 #define ZSWR0_RESET_STATUS ZSM_RESET_STINT
147 #define ZSWR0_RESET_TXINT ZSM_RESET_TXINT
148
149 /*
150 * Bits in Write Register 1 (`Transmit/Receive Interrupt and Data
151 * Transfer Mode Definition'). Note that bits 3 and 4 are taken together
152 * as a single unit, and bits 5 and 6 are useful only if bit 7 is set.
153 */
154 #define ZSWR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */
155 #define ZSWR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */
156 #define ZSWR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */
157 #define ZSWR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */
158
159 #define ZSWR1_RIE_NONE 0x00 /* disable rxint entirely */
160 #define ZSWR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */
161 #define ZSWR1_RIE 0x10 /* rxint per char & on S.C. */
162 #define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */
163
164 #define ZSWR1_PE_SC 0x04 /* parity error is special condition */
165 #define ZSWR1_TIE 0x02 /* transmit interrupt enable */
166 #define ZSWR1_SIE 0x01 /* external/status interrupt enable */
167
168 #define ZSWR1_IMASK 0x1F /* mask of all itr. enable bits. */
169
170 /* HSIS compat */
171 #define ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX)
172
173 /*
174 * Bits in Write Register 3 (`Receive Parameters and Control').
175 * Bits 7 and 6 are taken as a unit. Note that the receive bits
176 * per character ordering is insane.
177 *
178 * Here `hardware flow control' means CTS enables the transmitter
179 * and DCD enables the receiver. The latter is neither interesting
180 * nor useful, and gets in our way, making it almost unusable.
181 */
182 #define ZSWR3_RX_5 0x00 /* receive 5 bits per char */
183 #define ZSWR3_RX_7 0x40 /* receive 7 bits per char */
184 #define ZSWR3_RX_6 0x80 /* receive 6 bits per char */
185 #define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */
186 #define ZSWR3_RXSIZE 0xc0 /* receive char size mask */
187
188 #define ZSWR3_HFC 0x20 /* hardware flow control */
189 #define ZSWR3_HUNT 0x10 /* enter hunt mode */
190 #define ZSWR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */
191 #define ZSWR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */
192 #define ZSWR3_SDLC_SHORT_ADDR 0x02 /* short address mode (SDLC only) */
193 #define ZSWR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */
194 #define ZSWR3_RX_ENABLE 0x01 /* receiver enable */
195
196 /*
197 * Bits in Write Register 4 (`Transmit/Receive Miscellaneous Parameters
198 * and Modes'). Bits 7&6, 5&4, and 3&2 are taken as units.
199 */
200 #define ZSWR4_CLK_X1 0x00 /* clock divisor = 1 */
201 #define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */
202 #define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */
203 #define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */
204 #define ZSWR4_CLK_MASK 0xc0 /* clock divisor mask */
205
206 #define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */
207 #define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */
208 #define ZSWR4_SDLC 0x20 /* SDLC mode */
209 #define ZSWR4_EXTSYNC 0x30 /* external sync mode */
210 #define ZSWR4_SYNC_MASK 0x30 /* sync mode bit mask */
211
212 #define ZSWR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */
213 #define ZSWR4_ONESB 0x04 /* 1 stop bit */
214 #define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */
215 #define ZSWR4_TWOSB 0x0c /* 2 stop bits */
216 #define ZSWR4_SBMASK 0x0c /* mask of all stop bits */
217
218 #define ZSWR4_EVENP 0x02 /* check for even parity */
219 #define ZSWR4_PARENB 0x01 /* enable parity checking */
220 #define ZSWR4_PARMASK 0x03 /* mask of all parity bits */
221
222 /*
223 * Bits in Write Register 5 (`Transmit Parameter and Controls').
224 * Bits 6 and 5 are taken as a unit; the ordering is, as with RX
225 * bits per char, not sensible.
226 */
227 #define ZSWR5_DTR 0x80 /* assert (set to -12V) DTR */
228
229 #define ZSWR5_TX_5 0x00 /* transmit 5 or fewer bits */
230 #define ZSWR5_TX_7 0x20 /* transmit 7 bits */
231 #define ZSWR5_TX_6 0x40 /* transmit 6 bits */
232 #define ZSWR5_TX_8 0x60 /* transmit 8 bits */
233 #define ZSWR5_TXSIZE 0x60 /* transmit char size mask */
234
235 #define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */
236 #define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */
237 #define ZSWR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */
238 #define ZSWR5_RTS 0x02 /* assert RTS */
239 #define ZSWR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */
240
241 #ifdef not_done_here
242 /*
243 * Bits in Write Register 7 when the chip is in SDLC mode.
244 */
245 #define ZSWR7_SDLCFLAG 0x7e /* this value makes SDLC mode work */
246 #endif
247
248 /*
249 * Bits in Write Register 7' (ZSWR_ENHANCED above). This register is
250 * only available on the 85230. Dispite the fact it contains flags
251 * and not a single value, the register was named as it is read
252 * via RR14. Weird.
253 */
254 /* 0x80 unused */
255 #define ZSWR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */
256 #define ZSWR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */
257 #define ZSWR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */
258 #define ZSWR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */
259 #define ZSWR7P_RTS_DEACT 0x04 /* automatically deassert RTS */
260 #define ZSWR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */
261 #define ZSWR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */
262
263 /*
264 * Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6
265 * are taken as a unit and indicate the type of reset; 00 means no reset
266 * (and is not defined here).
267 */
268 #define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */
269 #define ZSWR9_A_RESET 0x80 /* reset channel A (0) */
270 #define ZSWR9_B_RESET 0x40 /* reset channel B (1) */
271 #define ZSWR9_SOFT_INTAC 0x20 /* Not in NMOS version */
272
273 #define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */
274 #define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */
275 #define ZSWR9_DLC 0x04 /* disable lower chain */
276 #define ZSWR9_NO_VECTOR 0x02 /* no vector */
277 #define ZSWR9_VECTOR_INCL_STAT 0x01 /* vector includes status */
278
279 /*
280 * Bits in Write Register 10 (`Miscellaneous Transmitter/Receiver Control
281 * Bits'). Bits 6 & 5 are taken as a unit, and some of the bits are
282 * meaningful only in certain modes. Bleah.
283 */
284 #define ZSWR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */
285
286 #define ZSWR10_NRZ 0x00 /* NRZ encoding */
287 #define ZSWR10_NRZI 0x20 /* NRZI encoding */
288 #define ZSWR10_FM1 0x40 /* FM1 encoding */
289 #define ZSWR10_FM0 0x60 /* FM0 encoding */
290
291 #define ZSWR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */
292 #define ZSWR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */
293 #define ZSWR10_ABORT_ON_UNDERRUN 0x4 /* abort on xmit underrun (SDLC) */
294 #define ZSWR10_LOOP_MODE 0x02 /* loop mode (SDLC) */
295 #define ZSWR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */
296
297 /*
298 * Bits in Write Register 11 (`Clock Mode Control'). Bits 6&5, 4&3, and
299 * 1&0 are taken as units. Various bits depend on other bits in complex
300 * ways; see the Zilog manual.
301 */
302 #define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */
303 /* (else have TTL oscil. on RTxC*) */
304 #define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */
305 #define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */
306 #define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */
307 #define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */
308
309 #define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */
310 #define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */
311 #define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */
312 #define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */
313
314 #define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */
315 /* (unless it is being used above) */
316 #define ZSWR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */
317 #define ZSWR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */
318 #define ZSWR11_TRXC_BAUD 0x02 /* TRxC output from BRG */
319 #define ZSWR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */
320
321 /*
322 * Formula for Write Registers 12 and 13 (`Lower Byte of Baud Rate
323 * Generator Time Constant' and `Upper Byte of ...'). Inputs:
324 *
325 * f BRG input clock frequency (in Hz) AFTER division
326 * by 1, 16, 32, or 64 (per clock divisor in WR4)
327 * bps desired rate in bits per second (9600, etc)
328 *
329 * We want
330 *
331 * f
332 * ----- + 0.5 - 2
333 * 2 bps
334 *
335 * rounded down to an integer. This can be computed entirely
336 * in integer arithmetic as:
337 *
338 * f + bps
339 * ------- - 2
340 * 2 bps
341 */
342 #define BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2)
343
344 /* inverse of above: given a BRG Time Constant, return Bits Per Second */
345 #define TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2))
346
347 /*
348 * Bits in Write Register 14 (`Miscellaneous Control Bits').
349 * Bits 7 through 5 are taken as a unit and make up a `DPLL command'.
350 */
351 #define ZSWR14_DPLL_NOOP 0x00 /* leave DPLL alone */
352 #define ZSWR14_DPLL_SEARCH 0x20 /* enter search mode */
353 #define ZSWR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */
354 #define ZSWR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */
355 #define ZSWR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */
356 #define ZSWR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */
357 #define ZSWR14_DPLL_FM 0xc0 /* operate in FM mode */
358 #define ZSWR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */
359
360 #define ZSWR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */
361 #define ZSWR14_AUTO_ECHO 0x08 /* set auto echo mode */
362 #define ZSWR14_DTR_REQ 0x04 /* DTR* / REQ* pin gives REQ* */
363 #define ZSWR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */
364 /* (else from RTxC* pin or xtal osc) */
365 #define ZSWR14_BAUD_ENA 0x01 /* enable BRG countdown */
366
367 /*
368 * Bits in Write Register 15 (`External/Status Interrupt Control').
369 * Most of these cause status interrupts whenever the corresponding
370 * bit or pin changes state (i.e., any rising or falling edge).
371 *
372 * NOTE: ZSWR15_SDLC_FIFO & ZSWR15_ENABLE_ENHANCED should not be
373 * set on an NMOS 8530. Also, ZSWR15_ENABLE_ENHANCED is only
374 * available on the 85230.
375 */
376 #define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */
377 #define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */
378 #define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */
379 #define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */
380 #define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */
381 #define ZSWR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */
382 #define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */
383 #define ZSWR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */
384
385 /*
386 * Bits in Read Register 0 (`Transmit/Receive Buffer Status and External
387 * Status').
388 */
389 #define ZSRR0_BREAK 0x80 /* break/abort detected */
390 #define ZSRR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */
391 #define ZSRR0_CTS 0x20 /* clear to send */
392 #define ZSRR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */
393 #define ZSRR0_DCD 0x08 /* data carrier detect */
394 #define ZSRR0_TX_READY 0x04 /* transmit buffer empty */
395 #define ZSRR0_ZERO_COUNT 0x02 /* zero count in baud clock */
396 #define ZSRR0_RX_READY 0x01 /* received character ready */
397
398 /*
399 * Bits in Read Register 1 (the Zilog book does not name this one).
400 */
401 #define ZSRR1_EOF 0x80 /* end of frame (SDLC mode) */
402 #define ZSRR1_FE 0x40 /* CRC/framing error */
403 #define ZSRR1_DO 0x20 /* data (receiver) overrun */
404 #define ZSRR1_PE 0x10 /* parity error */
405 #define ZSRR1_RC0 0x08 /* residue code 0 (SDLC mode) */
406 #define ZSRR1_RC1 0x04 /* residue code 1 (SDLC mode) */
407 #define ZSRR1_RC2 0x02 /* residue code 2 (SDLC mode) */
408 #define ZSRR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */
409
410 /*
411 * Read Register 2 in B channel contains status bits if VECTOR_INCL_STAT
412 * is set.
413 */
414
415 /*
416 * Bits in Read Register 3 (`Interrupt Pending'). Only channel A
417 * has an RR3.
418 */
419 /* 0x80 unused, returned as 0 */
420 /* 0x40 unused, returned as 0 */
421 #define ZSRR3_IP_A_RX 0x20 /* channel A recv int pending */
422 #define ZSRR3_IP_A_TX 0x10 /* channel A xmit int pending */
423 #define ZSRR3_IP_A_STAT 0x08 /* channel A status int pending */
424 #define ZSRR3_IP_B_RX 0x04 /* channel B recv int pending */
425 #define ZSRR3_IP_B_TX 0x02 /* channel B xmit int pending */
426 #define ZSRR3_IP_B_STAT 0x01 /* channel B status int pending */
427
428 /*
429 * Bits in Read Register 10 (`contains some miscellaneous status bits').
430 */
431 #define ZSRR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */
432 #define ZSRR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */
433 /* 0x20 unused */
434 #define ZSRR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */
435 /* 0x08 unused */
436 /* 0x04 unused */
437 #define ZSRR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */
438
439 /*
440 * Bits in Read Register 15. This register is one of the few that
441 * simply reads back the corresponding Write Register.
442 */
443 #define ZSRR15_BREAK_IE 0x80 /* break/abort status int enable */
444 #define ZSRR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */
445 #define ZSRR15_CTS_IE 0x20 /* CTS* pin status int enable */
446 #define ZSRR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */
447 #define ZSRR15_DCD_IE 0x08 /* DCD* pin status int enable */
448 /* 0x04 unused, returned as zero */
449 #define ZSRR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */
450 /* 0x01 unused, returned as zero */
451
452 #endif /* Z8530REG_H */

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