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/* gxemul: $Id: wdsc_sbicreg.h,v 1.2 2005/03/05 12:34:03 debug Exp $ */ |
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/* $NetBSD: sbicreg.h,v 1.4 2002/03/13 13:12:27 simonb Exp $ */ |
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|
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/* |
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* Copyright (c) 2001 Wayne Knowles |
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* Copyright (c) 1990 The Regents of the University of California. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* Van Jacobson of Lawrence Berkeley Laboratory. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)scsireg.h 7.3 (Berkeley) 2/5/91 |
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*/ |
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|
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/* |
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* WD33C93 SCSI interface hardware description. |
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* |
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* Using parts of the Mach scsi driver for the 33C93 |
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*/ |
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|
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#define SBIC_myid 0 |
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#define SBIC_cdbsize 0 |
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#define SBIC_control 1 |
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#define SBIC_timeo 2 |
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#define SBIC_cdb1 3 |
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#define SBIC_tsecs 3 |
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#define SBIC_cdb2 4 |
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#define SBIC_theads 4 |
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#define SBIC_cdb3 5 |
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#define SBIC_tcyl_hi 5 |
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#define SBIC_cdb4 6 |
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#define SBIC_tcyl_lo 6 |
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#define SBIC_cdb5 7 |
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#define SBIC_addr_hi 7 |
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#define SBIC_cdb6 8 |
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#define SBIC_addr_2 8 |
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#define SBIC_cdb7 9 |
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#define SBIC_addr_3 9 |
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#define SBIC_cdb8 10 |
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#define SBIC_addr_lo 10 |
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#define SBIC_cdb9 11 |
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#define SBIC_secno 11 |
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#define SBIC_cdb10 12 |
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#define SBIC_headno 12 |
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#define SBIC_cdb11 13 |
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#define SBIC_cylno_hi 13 |
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#define SBIC_cdb12 14 |
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#define SBIC_cylno_lo 14 |
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#define SBIC_tlun 15 |
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#define SBIC_cmd_phase 16 |
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#define SBIC_syn 17 |
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#define SBIC_count_hi 18 |
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#define SBIC_count_med 19 |
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#define SBIC_count_lo 20 |
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#define SBIC_selid 21 |
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#define SBIC_rselid 22 |
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#define SBIC_csr 23 |
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#define SBIC_cmd 24 |
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#define SBIC_data 25 |
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#define SBIC_queue_tag 26 |
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#define SBIC_aux_status 27 |
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|
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/* wd33c93_asr is addressed directly */ |
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|
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/* |
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* Register defines |
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*/ |
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|
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/* |
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* Auxiliary Status Register |
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*/ |
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|
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#define SBIC_ASR_INT 0x80 /* Interrupt pending */ |
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#define SBIC_ASR_LCI 0x40 /* Last command ignored */ |
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#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */ |
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#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */ |
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#define SBIC_ASR_xxx 0x0c |
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#define SBIC_ASR_PE 0x02 /* Parity error (even) */ |
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#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */ |
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|
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/* |
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* My ID register, and/or CDB Size |
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*/ |
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|
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#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */ |
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/* 11 Mhz is invalid */ |
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#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */ |
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#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */ |
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#define SBIC_ID_RAF 0x20 /* */ |
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#define SBIC_ID_EHP 0x10 /* Enable host parity */ |
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#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */ |
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#define SBIC_ID_MASK 0x07 |
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#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */ |
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|
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/* |
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* Control register |
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*/ |
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|
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#define SBIC_CTL_DMA 0x80 /* Single byte dma */ |
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#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/ |
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#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */ |
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#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */ |
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#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */ |
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#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */ |
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#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/ |
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#define SBIC_CTL_HA 0x02 /* Halt on ATN */ |
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#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */ |
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|
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/* |
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* Timeout period register |
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* [val in msecs, input clk in 0.1 Mhz] |
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*/ |
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|
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#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1) |
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|
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/* |
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* CDBn registers, note that |
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* cdb11 is used for status byte in target mode (send-status-and-cc) |
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* cdb12 sez if linked command complete, and w/flag if so |
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*/ |
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|
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/* |
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* Target LUN register |
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* [holds target status when select-and-xfer] |
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*/ |
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|
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#define SBIC_TLUN_VALID 0x80 /* did we receive an Identify msg */ |
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#define SBIC_TLUN_DOK 0x40 /* Disconnect OK */ |
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#define SBIC_TLUN_xxx 0x38 |
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#define SBIC_TLUN_MASK 0x07 |
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|
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/* |
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* Command Phase register |
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*/ |
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|
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#define SBIC_CPH_MASK 0x7f /* values/restarts are cmd specific */ |
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#define SBIC_CPH(p) ((p) & SBIC_CPH_MASK) |
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|
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/* |
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* FIFO register |
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*/ |
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|
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#define SBIC_FIFO_DEEP 12 |
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|
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/* |
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* maximum possible size in TC registers. Since this is 24 bit, it's easy |
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*/ |
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#define SBIC_TC_MAX ((1 << 24) - 1) |
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|
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/* |
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* Synchronous xfer register |
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*/ |
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|
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#define SBIC_SYN_OFF_MASK 0x0f |
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#define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP |
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#define SBIC_SYN_PER_MASK 0x70 |
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#define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */ |
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|
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#define SBIC_SYN(o,p) \ |
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(((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK)) |
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|
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/* |
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* Transfer count register |
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* optimal access macros depend on addressing |
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*/ |
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|
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/* |
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* Destination ID (selid) register |
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*/ |
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|
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#define SBIC_SID_SCC 0x80 /* Select command chaining (tgt) */ |
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#define SBIC_SID_DPD 0x40 /* Data phase direction (inittor) */ |
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#define SBIC_SID_FROM_SCSI 0x40 |
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#define SBIC_SID_TO_SCSI 0x00 |
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#define SBIC_SID_xxx 0x38 |
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#define SBIC_SID_IDMASK 0x07 |
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|
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/* |
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* Source ID (rselid) register |
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*/ |
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|
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#define SBIC_RID_ER 0x80 /* Enable reselection */ |
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#define SBIC_RID_ES 0x40 /* Enable selection */ |
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#define SBIC_RID_DSP 0x20 /* Disable select parity */ |
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#define SBIC_RID_SIV 0x08 /* Source ID valid */ |
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#define SBIC_RID_MASK 0x07 |
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|
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/* |
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* Status register |
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*/ |
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|
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#define SBIC_CSR_CAUSE 0xf0 |
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#define SBIC_CSR_RESET 0x00 /* chip was reset */ |
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#define SBIC_CSR_CMD_DONE 0x10 /* cmd completed */ |
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#define SBIC_CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/ |
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#define SBIC_CSR_CMD_ERR 0x40 /* end with error */ |
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#define SBIC_CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */ |
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|
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|
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#define SBIC_CSR_QUALIFIER 0x0f |
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/* Reset State Interrupts */ |
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#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/ |
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#define SBIC_CSR_RESET_AM 0x01 /* reset w/advanced features*/ |
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/* Successful Completion Interrupts */ |
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#define SBIC_CSR_TARGET 0x10 /* reselect complete */ |
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#define SBIC_CSR_INITIATOR 0x11 /* select complete */ |
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#define SBIC_CSR_WO_ATN 0x13 /* tgt mode completion */ |
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#define SBIC_CSR_W_ATN 0x14 /* ditto */ |
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#define SBIC_CSR_XLATED 0x15 /* translate address cmd */ |
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#define SBIC_CSR_S_XFERRED 0x16 /* initiator mode completion*/ |
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#define SBIC_CSR_XFERRED 0x18 /* phase in low bits */ |
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/* Paused or Aborted Interrupts */ |
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#define SBIC_CSR_MSGIN_W_ACK 0x20 /* (I) msgin, ACK asserted*/ |
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#define SBIC_CSR_SDP 0x21 /* (I) SDP msg received */ |
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#define SBIC_CSR_SEL_ABRT 0x22 /* sel/resel aborted */ |
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#define SBIC_CSR_XFR_PAUSED 0x23 /* (T) no ATN */ |
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#define SBIC_CSR_XFR_PAUSED_ATN 0x24 /* (T) ATN is asserted */ |
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#define SBIC_CSR_RSLT_AM 0x27 /* (I) lost selection (AM) */ |
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#define SBIC_CSR_MIS 0x28 /* (I) xfer aborted, ph mis */ |
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/* Terminated Interrupts */ |
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#define SBIC_CSR_CMD_INVALID 0x40 |
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#define SBIC_CSR_DISC 0x41 /* (I) tgt disconnected */ |
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#define SBIC_CSR_SEL_TIMEO 0x42 |
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#define SBIC_CSR_PE 0x43 /* parity error */ |
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#define SBIC_CSR_PE_ATN 0x44 /* ditto, ATN is asserted */ |
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#define SBIC_CSR_XLATE_TOOBIG 0x45 |
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#define SBIC_CSR_RSLT_NOAM 0x46 /* (I) lost sel, no AM mode */ |
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#define SBIC_CSR_BAD_STATUS 0x47 /* status byte was nok */ |
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#define SBIC_CSR_MIS_1 0x48 /* ph mis, see low bits */ |
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/* Service Required Interrupts */ |
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#define SBIC_CSR_RSLT_NI 0x80 /* reselected, no ify msg */ |
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#define SBIC_CSR_RSLT_IFY 0x81 /* ditto, AM mode, got ify */ |
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#define SBIC_CSR_SLT 0x82 /* selected, no ATN */ |
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#define SBIC_CSR_SLT_ATN 0x83 /* selected with ATN */ |
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#define SBIC_CSR_ATN 0x84 /* (T) ATN asserted */ |
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#define SBIC_CSR_DISC_1 0x85 /* (I) bus is free */ |
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#define SBIC_CSR_UNK_GROUP 0x87 /* strange CDB1 */ |
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#define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */ |
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|
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#define SBIC_PHASE(csr) SCSI_PHASE(csr) |
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|
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/* |
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* Command register (command codes) |
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*/ |
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|
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#define SBIC_CMD_SBT 0x80 /* Single byte xfer qualifier */ |
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#define SBIC_CMD_MASK 0x7f |
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|
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/* Miscellaneous */ |
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#define SBIC_CMD_RESET 0x00 /* (DTI) lev I */ |
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#define SBIC_CMD_ABORT 0x01 /* (DTI) lev I */ |
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#define SBIC_CMD_DISC 0x04 /* ( TI) lev I */ |
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#define SBIC_CMD_SSCC 0x0d /* ( TI) lev I */ |
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#define SBIC_CMD_SET_IDI 0x0f /* (DTI) lev I */ |
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#define SBIC_CMD_XLATE 0x18 /* (DT ) lev II */ |
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|
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/* Initiator state */ |
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#define SBIC_CMD_SET_ATN 0x02 /* ( I) lev I */ |
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#define SBIC_CMD_CLR_ACK 0x03 /* ( I) lev I */ |
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#define SBIC_CMD_XFER_PAD 0x19 /* ( I) lev II */ |
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#define SBIC_CMD_XFER_INFO 0x20 /* ( I) lev II */ |
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|
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/* Target state */ |
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#define SBIC_CMD_SND_DISC 0x0e /* ( T ) lev II */ |
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#define SBIC_CMD_RCV_CMD 0x10 /* ( T ) lev II */ |
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#define SBIC_CMD_RCV_DATA 0x11 /* ( T ) lev II */ |
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#define SBIC_CMD_RCV_MSG_OUT 0x12 /* ( T ) lev II */ |
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#define SBIC_CMD_RCV 0x13 /* ( T ) lev II */ |
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#define SBIC_CMD_SND_STATUS 0x14 /* ( T ) lev II */ |
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#define SBIC_CMD_SND_DATA 0x15 /* ( T ) lev II */ |
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#define SBIC_CMD_SND_MSG_IN 0x16 /* ( T ) lev II */ |
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#define SBIC_CMD_SND 0x17 /* ( T ) lev II */ |
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|
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/* Disconnected state */ |
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#define SBIC_CMD_RESELECT 0x05 /* (D ) lev II */ |
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#define SBIC_CMD_SEL_ATN 0x06 /* (D ) lev II */ |
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#define SBIC_CMD_SEL 0x07 /* (D ) lev II */ |
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#define SBIC_CMD_SEL_ATN_XFER 0x08 /* (D I) lev II */ |
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#define SBIC_CMD_SEL_XFER 0x09 /* (D I) lev II */ |
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#define SBIC_CMD_RESELECT_RECV 0x0a /* (DT ) lev II */ |
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#define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */ |
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#define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */ |
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|
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|
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#define PHASE_MASK 0x07 /* mask for psns/pctl phase */ |
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#define DATA_OUT_PHASE 0x00 |
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#define DATA_IN_PHASE 0x01 |
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#define CMD_PHASE 0x02 |
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#define STATUS_PHASE 0x03 |
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#define BUS_FREE_PHASE 0x04 |
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#define ARB_SEL_PHASE 0x05 /* Fuji chip combines bus arb with sel. */ |
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#define MESG_OUT_PHASE 0x06 |
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#define MESG_IN_PHASE 0x07 |
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|
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#define SCSI_PHASE(reg) ((reg) & PHASE_MASK) |
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|
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#define SCSI_STATUS_MASK 0x3e /* Mask unused bits in status byte */ |
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|
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/* approximate, but we won't do SBT on selects */ |
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#define wd33c93_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa)) |
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|
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#define PAD(n) char n; |
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#define SBIC_MACHINE_DMA_MODE SBIC_CTL_DMA |
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|
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typedef struct { |
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volatile unsigned char wd33c93_asr; /* r : Aux Status Register */ |
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#define wd33c93_address wd33c93_asr /* w : desired register no */ |
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volatile unsigned char wd33c93_value; /* rw: register value */ |
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} wd33c93_padded_ind_regmap_t; |
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typedef volatile wd33c93_padded_ind_regmap_t *wd33c93_regmap_p; |
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|
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#define SBIC_ASR 0 /* offset to ASC register */ |
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#define SBIC_ADDR 0 /* offset to address reg */ |
| 342 |
#define SBIC_VAL 1 /* offset to data register */ |
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|
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#define wd33c93_read_reg(sc,regno,val) \ |
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do { \ |
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bus_space_write_1((sc)->sc_regt,(sc)->sc_regh,SBIC_ADDR,(regno)); \ |
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(val) = bus_space_read_1((sc)->sc_regt,(sc)->sc_regh,SBIC_VAL); \ |
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} while (0) |
| 349 |
|
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#define wd33c93_write_reg(sc,regno,val) \ |
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do { \ |
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bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, SBIC_ADDR, (regno)); \ |
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bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, SBIC_VAL, (val)); \ |
| 354 |
} while (0) |
| 355 |
|
| 356 |
#define SET_SBIC_myid(sc,val) wd33c93_write_reg(sc,SBIC_myid,val) |
| 357 |
#define GET_SBIC_myid(sc,val) wd33c93_read_reg(sc,SBIC_myid,val) |
| 358 |
#define SET_SBIC_cdbsize(sc,val) wd33c93_write_reg(sc,SBIC_cdbsize,val) |
| 359 |
#define GET_SBIC_cdbsize(sc,val) wd33c93_read_reg(sc,SBIC_cdbsize,val) |
| 360 |
#define SET_SBIC_control(sc,val) wd33c93_write_reg(sc,SBIC_control,val) |
| 361 |
#define GET_SBIC_control(sc,val) wd33c93_read_reg(sc,SBIC_control,val) |
| 362 |
#define SET_SBIC_timeo(sc,val) wd33c93_write_reg(sc,SBIC_timeo,val) |
| 363 |
#define GET_SBIC_timeo(sc,val) wd33c93_read_reg(sc,SBIC_timeo,val) |
| 364 |
#define SET_SBIC_cdb1(sc,val) wd33c93_write_reg(sc,SBIC_cdb1,val) |
| 365 |
#define GET_SBIC_cdb1(sc,val) wd33c93_read_reg(sc,SBIC_cdb1,val) |
| 366 |
#define SET_SBIC_cdb2(sc,val) wd33c93_write_reg(sc,SBIC_cdb2,val) |
| 367 |
#define GET_SBIC_cdb2(sc,val) wd33c93_read_reg(sc,SBIC_cdb2,val) |
| 368 |
#define SET_SBIC_cdb3(sc,val) wd33c93_write_reg(sc,SBIC_cdb3,val) |
| 369 |
#define GET_SBIC_cdb3(sc,val) wd33c93_read_reg(sc,SBIC_cdb3,val) |
| 370 |
#define SET_SBIC_cdb4(sc,val) wd33c93_write_reg(sc,SBIC_cdb4,val) |
| 371 |
#define GET_SBIC_cdb4(sc,val) wd33c93_read_reg(sc,SBIC_cdb4,val) |
| 372 |
#define SET_SBIC_cdb5(sc,val) wd33c93_write_reg(sc,SBIC_cdb5,val) |
| 373 |
#define GET_SBIC_cdb5(sc,val) wd33c93_read_reg(sc,SBIC_cdb5,val) |
| 374 |
#define SET_SBIC_cdb6(sc,val) wd33c93_write_reg(sc,SBIC_cdb6,val) |
| 375 |
#define GET_SBIC_cdb6(sc,val) wd33c93_read_reg(sc,SBIC_cdb6,val) |
| 376 |
#define SET_SBIC_cdb7(sc,val) wd33c93_write_reg(sc,SBIC_cdb7,val) |
| 377 |
#define GET_SBIC_cdb7(sc,val) wd33c93_read_reg(sc,SBIC_cdb7,val) |
| 378 |
#define SET_SBIC_cdb8(sc,val) wd33c93_write_reg(sc,SBIC_cdb8,val) |
| 379 |
#define GET_SBIC_cdb8(sc,val) wd33c93_read_reg(sc,SBIC_cdb8,val) |
| 380 |
#define SET_SBIC_cdb9(sc,val) wd33c93_write_reg(sc,SBIC_cdb9,val) |
| 381 |
#define GET_SBIC_cdb9(sc,val) wd33c93_read_reg(sc,SBIC_cdb9,val) |
| 382 |
#define SET_SBIC_cdb10(sc,val) wd33c93_write_reg(sc,SBIC_cdb10,val) |
| 383 |
#define GET_SBIC_cdb10(sc,val) wd33c93_read_reg(sc,SBIC_cdb10,val) |
| 384 |
#define SET_SBIC_cdb11(sc,val) wd33c93_write_reg(sc,SBIC_cdb11,val) |
| 385 |
#define GET_SBIC_cdb11(sc,val) wd33c93_read_reg(sc,SBIC_cdb11,val) |
| 386 |
#define SET_SBIC_cdb12(sc,val) wd33c93_write_reg(sc,SBIC_cdb12,val) |
| 387 |
#define GET_SBIC_cdb12(sc,val) wd33c93_read_reg(sc,SBIC_cdb12,val) |
| 388 |
#define SET_SBIC_tlun(sc,val) wd33c93_write_reg(sc,SBIC_tlun,val) |
| 389 |
#define GET_SBIC_tlun(sc,val) wd33c93_read_reg(sc,SBIC_tlun,val) |
| 390 |
#define SET_SBIC_cmd_phase(sc,val) wd33c93_write_reg(sc,SBIC_cmd_phase,val) |
| 391 |
#define GET_SBIC_cmd_phase(sc,val) wd33c93_read_reg(sc,SBIC_cmd_phase,val) |
| 392 |
#define SET_SBIC_syn(sc,val) wd33c93_write_reg(sc,SBIC_syn,val) |
| 393 |
#define GET_SBIC_syn(sc,val) wd33c93_read_reg(sc,SBIC_syn,val) |
| 394 |
#define SET_SBIC_count_hi(sc,val) wd33c93_write_reg(sc,SBIC_count_hi,val) |
| 395 |
#define GET_SBIC_count_hi(sc,val) wd33c93_read_reg(sc,SBIC_count_hi,val) |
| 396 |
#define SET_SBIC_count_med(sc,val) wd33c93_write_reg(sc,SBIC_count_med,val) |
| 397 |
#define GET_SBIC_count_med(sc,val) wd33c93_read_reg(sc,SBIC_count_med,val) |
| 398 |
#define SET_SBIC_count_lo(sc,val) wd33c93_write_reg(sc,SBIC_count_lo,val) |
| 399 |
#define GET_SBIC_count_lo(sc,val) wd33c93_read_reg(sc,SBIC_count_lo,val) |
| 400 |
#define SET_SBIC_selid(sc,val) wd33c93_write_reg(sc,SBIC_selid,val) |
| 401 |
#define GET_SBIC_selid(sc,val) wd33c93_read_reg(sc,SBIC_selid,val) |
| 402 |
#define SET_SBIC_rselid(sc,val) wd33c93_write_reg(sc,SBIC_rselid,val) |
| 403 |
#define GET_SBIC_rselid(sc,val) wd33c93_read_reg(sc,SBIC_rselid,val) |
| 404 |
#define SET_SBIC_csr(sc,val) wd33c93_write_reg(sc,SBIC_csr,val) |
| 405 |
#define GET_SBIC_csr(sc,val) wd33c93_read_reg(sc,SBIC_csr,val) |
| 406 |
#define SET_SBIC_cmd(sc,val) wd33c93_write_reg(sc,SBIC_cmd,val) |
| 407 |
#define GET_SBIC_cmd(sc,val) wd33c93_read_reg(sc,SBIC_cmd,val) |
| 408 |
#define SET_SBIC_data(sc,val) wd33c93_write_reg(sc,SBIC_data,val) |
| 409 |
#define GET_SBIC_data(sc,val) wd33c93_read_reg(sc,SBIC_data,val) |
| 410 |
#define SET_SBIC_queue_tag(sc,val) wd33c93_write_reg(sc,SBIC_queue_tag,val) |
| 411 |
#define GET_SBIC_queue_tag(sc,val) wd33c93_read_reg(sc,SBIC_queue_tag,val) |
| 412 |
|
| 413 |
#define SBIC_TC_PUT(sc,val) \ |
| 414 |
do { \ |
| 415 |
wd33c93_write_reg(sc,SBIC_count_hi,((val)>>16)); \ |
| 416 |
bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, \ |
| 417 |
SBIC_VAL, (val)>>8); \ |
| 418 |
bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, \ |
| 419 |
SBIC_VAL, (val)); \ |
| 420 |
} while (0) |
| 421 |
|
| 422 |
#define SBIC_TC_GET(sc,val) \ |
| 423 |
do { \ |
| 424 |
wd33c93_read_reg(sc,SBIC_count_hi,(val)); \ |
| 425 |
(val) = ((val)<<8) | bus_space_read_1((sc)->sc_regt, \ |
| 426 |
(sc)->sc_regh,SBIC_VAL); \ |
| 427 |
(val) = ((val)<<8) | bus_space_read_1((sc)->sc_regt, \ |
| 428 |
(sc)->sc_regh,SBIC_VAL); \ |
| 429 |
} while (0) |
| 430 |
|
| 431 |
#define SBIC_LOAD_COMMAND(sc,cmd,cmdsize) \ |
| 432 |
do { \ |
| 433 |
int n = (cmdsize) - 1; \ |
| 434 |
char *ptr = (char *)(cmd); \ |
| 435 |
wd33c93_write_reg(regs, SBIC_cdb1, *ptr++); \ |
| 436 |
while(n-- > 0) \ |
| 437 |
bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, \ |
| 438 |
SBIC_VAL, *ptr++); /* XXX write_multi */ \ |
| 439 |
} while (0) |
| 440 |
|
| 441 |
#define GET_SBIC_asr(sc,val) \ |
| 442 |
do { \ |
| 443 |
(val) = bus_space_read_1((sc)->sc_regt,(sc)->sc_regh,SBIC_ASR); \ |
| 444 |
} while (0) |
| 445 |
|
| 446 |
|
| 447 |
#define WAIT_CIP(sc) \ |
| 448 |
do { \ |
| 449 |
while (bus_space_read_1((sc)->sc_regt,(sc)->sc_regh, \ |
| 450 |
SBIC_ASR) & SBIC_ASR_CIP) \ |
| 451 |
/*nop*/; \ |
| 452 |
} while (0) |
| 453 |
|
| 454 |
/* |
| 455 |
* transmit a byte in programmed I/O mode |
| 456 |
*/ |
| 457 |
#define SEND_BYTE(sc, ch) \ |
| 458 |
do { \ |
| 459 |
WAIT_CIP(sc); \ |
| 460 |
SET_SBIC_cmd(sc, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ |
| 461 |
SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \ |
| 462 |
SET_SBIC_data(sc, ch); \ |
| 463 |
} while (0) |
| 464 |
|
| 465 |
/* |
| 466 |
* receive a byte in programmed I/O mode |
| 467 |
*/ |
| 468 |
#define RECV_BYTE(sc, ch) \ |
| 469 |
do { \ |
| 470 |
WAIT_CIP(sc); \ |
| 471 |
SET_SBIC_cmd(sc, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ |
| 472 |
SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \ |
| 473 |
GET_SBIC_data(sc, ch); \ |
| 474 |
} while (0) |
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