/[gxemul]/trunk/src/include/vripreg.h
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Contents of /trunk/src/include/vripreg.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 11805 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============
1 /* gxemul: $Id: vripreg.h,v 1.1 2005/04/06 17:13:44 debug Exp $ */
2 /* $NetBSD: vripreg.h,v 1.8 2003/04/01 02:33:52 igy Exp $ */
3
4 #ifndef VRIPREG_H
5 #define VRIPREG_H
6
7 /*-
8 * Copyright (c) 1999
9 * Shin Takemura and PocketBSD Project. All rights reserved.
10 * Copyright (c) 2001 SATO Kazumi, All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the PocketBSD project
23 * and its contributors.
24 * 4. Neither the name of the project nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 */
41
42 #define VRIP_NO_ADDR 0x00000000
43 /*
44 * VR4181 registers
45 */
46 #define VR4181_BCU_ADDR 0x0a000000
47 #define VR4181_DMAAU_ADDR VRIP_NO_ADDR
48 #define VR4181_DCU_ADDR VRIP_NO_ADDR
49 #define VR4181_CMU_ADDR 0x0a000004
50 #define VR4181_ICU_ADDR 0x0a000080
51 #define VR4181_PMU_ADDR 0x0a0000a0
52 #define VR4181_RTC_ADDR 0x0a0000c0
53 #define VR4181_DSU_ADDR 0x0a0000e0
54 #define VR4181_GIU_ADDR VRIP_NO_ADDR /* XXX: no register */
55 #define VR4181_PIU_ADDR 0x0a000122
56 #define VR4181_AIU_ADDR 0x0a000160
57 #define VR4181_KIU_ADDR 0x0a000180
58 #define VR4181_DSIU_ADDR 0x0a0001a0
59 #define VR4181_LED_ADDR 0x0a000240
60 #define VR4181_SIU_ADDR 0x0c000010
61 #define VR4181_HSP_ADDR 0x0a000020
62 #define VR4181_FIR_ADDR 0x0a000000 /* XXX */
63 #define VR4181_MEMCON_ADDR 0x0a000300
64 #define VR4181_ISABRG_ADDR 0x0b0002c0
65 #define VR4181_ECU_ADDR 0x0b0008e0
66 #define VR4181_DCU81_ADDR 0x0a000020
67 #define VR4181_CSI81_ADDR 0x0b000900
68 #define VR4181_GIU81_ADDR 0x0b000300
69 #define VR4181_LCD_ADDR 0x0a000400
70 #define VR4181_SIU1_ADDR 0x0c000000
71 #define VR4181_SCU_ARR VRIP_NO_ADDR /* XXX: no register */
72 #define VR4181_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */
73 #define VR4181_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */
74 #define VR4181_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */
75 #define VR4181_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */
76
77 /*
78 * VR4101-4121 registers
79 */
80 #define VR4102_BCU_ADDR 0x0b000000
81 #define VR4102_DMAAU_ADDR 0x0b000020
82 #define VR4102_DCU_ADDR 0x0b000040
83 #define VR4102_CMU_ADDR 0x0b000060
84 #define VR4102_ICU_ADDR 0x0b000080
85 #define VR4102_PMU_ADDR 0x0b0000a0
86 #define VR4102_RTC_ADDR 0x0b0000c0
87 #define VR4102_DSU_ADDR 0x0b0000e0
88 #define VR4102_GIU_ADDR 0x0b000100
89 #define VR4102_PIU_ADDR 0x0b000120
90 #define VR4102_AIU_ADDR 0x0b000160
91 #define VR4102_KIU_ADDR 0x0b000180
92 #define VR4102_DSIU_ADDR 0x0b0001a0
93 #define VR4102_LED_ADDR 0x0b000240
94 #define VR4102_SIU_ADDR 0x0c000000
95 #define VR4102_HSP_ADDR 0x0c000020
96 #define VR4102_FIR_ADDR 0x0b000000 /* XXX */
97 #define VR4102_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */
98 #define VR4102_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */
99 #define VR4102_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */
100 #define VR4102_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */
101 #define VR4102_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */
102 #define VR4102_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */
103 #define VR4102_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */
104 #define VR4102_SCU_ARR VRIP_NO_ADDR /* XXX: no register */
105 #define VR4102_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */
106 #define VR4102_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */
107 #define VR4102_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */
108 #define VR4102_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */
109 /*
110 * VR4122 registers
111 */
112 #define VR4122_BCU_ADDR 0x0f000000
113 #define VR4122_DMAAU_ADDR 0x0f000020
114 #define VR4122_DCU_ADDR 0x0f000040
115 #define VR4122_CMU_ADDR 0x0f000060
116 #define VR4122_ICU_ADDR 0x0f000080
117 #define VR4122_PMU_ADDR 0x0f0000c0
118 #define VR4122_RTC_ADDR 0x0f000100
119 #define VR4122_DSU_ADDR VRIP_NO_ADDR /* XXX: no register */
120 #define VR4122_GIU_ADDR 0x0f000140
121 #define VR4122_PIU_ADDR VRIP_NO_ADDR /* XXX: no register */
122 #define VR4122_AIU_ADDR VRIP_NO_ADDR /* XXX: no register */
123 #define VR4122_KIU_ADDR VRIP_NO_ADDR /* XXX: no register */
124 #define VR4122_DSIU_ADDR 0x0f000820
125 #define VR4122_LED_ADDR 0x0f000180
126 #define VR4122_SIU_ADDR 0x0f000800
127 #define VR4122_HSP_ADDR VRIP_NO_ADDR /* XXX: no register */
128 #define VR4122_FIR_ADDR 0x0f000840 /* XXX */
129 #define VR4122_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */
130 #define VR4122_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */
131 #define VR4122_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */
132 #define VR4122_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */
133 #define VR4122_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */
134 #define VR4122_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */
135 #define VR4122_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */
136 #define VR4122_SCU_ARR 0x0f001000
137 #define VR4122_SDRAMU_ADDR 0x0f000400
138 #define VR4122_PCI_ADDR 0x0f000c00
139 #define VR4122_PCICONF_ADDR 0x0f000d00
140 #define VR4122_CSI_ADDR 0x0f0001a0
141
142 /*
143 * VRIP base address
144 *
145 * REQUIRE: opt_vr41xx.h, vrcpudef.h
146 */
147 #if 0
148 #include "opt_vr41xx.h"
149 #include <hpcmips/vr/vrcpudef.h>
150 #endif
151
152 #if defined SINGLE_VRIP_BASE
153
154 #if defined VRGROUP_4181
155 #define VRIP_BASE_ADDR 0x0a000000
156
157 #define VRIP_BCU_ADDR VR4181_BCU_ADDR
158 #define VRIP_DMAAU_ADDR VR4181_DMAAU_ADDR
159 #define VRIP_DCU_ADDR VR4181_DCU_ADDR
160 #define VRIP_CMU_ADDR VR4181_CMU_ADDR
161 #define VRIP_ICU_ADDR VR4181_ICU_ADDR
162 #define VRIP_PMU_ADDR VR4181_PMU_ADDR
163 #define VRIP_RTC_ADDR VR4181_RTC_ADDR
164 #define VRIP_DSU_ADDR VR4181_DSU_ADDR
165 #define VRIP_GIU_ADDR VR4181_GIU_ADDR
166 #define VRIP_PIU_ADDR VR4181_PIU_ADDR
167 #define VRIP_AIU_ADDR VR4181_AIU_ADDR
168 #define VRIP_KIU_ADDR VR4181_KIU_ADDR
169 #define VRIP_DSIU_ADDR VR4181_DSIU_ADDR
170 #define VRIP_LED_ADDR VR4181_LED_ADDR
171 #define VRIP_SIU_ADDR VR4181_SIU_ADDR
172 #define VRIP_HSP_ADDR VR4181_HSP_ADDR
173 #define VRIP_FIR_ADDR VR4181_FIR_ADDR
174 #define VRIP_MEMCON_ADDR VR4181_MEMCON_ADDR
175 #define VRIP_ISABRG_ADDR VR4181_ISABRG_ADDR
176 #define VRIP_ECU_ADDR VR4181_ECU_ADDR
177 #define VRIP_DCU81_ADDR VR4181_DCU81_ADDR
178 #define VRIP_CSI81_ADDR VR4181_CSI81_ADDR
179 #define VRIP_GIU81_ADDR VR4181_GIU81_ADDR
180 #define VRIP_LCD_ADDR VR4181_LCD_ADDR
181 #define VRIP_SIU1_ADDR VR4181_SIU1_ADDR
182 #define VRIP_SCU_ARR VR4181_SCU_ARR /* XXX: no register */
183 #define VRIP_SDRAMU_ADDR VR4181_SDRAMU_ADDR /* XXX: no register */
184 #define VRIP_PCI_ADDR VR4181_PCI_ADDR /* XXX: no register */
185 #define VRIP_PCICONF_ADDR VR4181_PCICONF_ADDR /* XXX: no register */
186 #define VRIP_CSI_ADDR VR4181_CSI_ADDR /* XXX: no register */
187
188 #endif /* VRGROUP_4181 */
189
190 #if defined VRGROUP_4122_4131
191 #define VRIP_BASE_ADDR 0x0f000000
192
193 #define VRIP_BCU_ADDR VR4122_BCU_ADDR
194 #define VRIP_DMAAU_ADDR VR4122_DMAAU_ADDR
195 #define VRIP_DCU_ADDR VR4122_DCU_ADDR
196 #define VRIP_CMU_ADDR VR4122_CMU_ADDR
197 #define VRIP_ICU_ADDR VR4122_ICU_ADDR
198 #define VRIP_PMU_ADDR VR4122_PMU_ADDR
199 #define VRIP_RTC_ADDR VR4122_RTC_ADDR
200 #define VRIP_DSU_ADDR VR4122_DSU_ADDR
201 #define VRIP_GIU_ADDR VR4122_GIU_ADDR
202 #define VRIP_PIU_ADDR VR4122_PIU_ADDR
203 #define VRIP_AIU_ADDR VR4122_AIU_ADDR
204 #define VRIP_KIU_ADDR VR4122_KIU_ADDR
205 #define VRIP_DSIU_ADDR VR4122_DSIU_ADDR
206 #define VRIP_LED_ADDR VR4122_LED_ADDR
207 #define VRIP_SIU_ADDR VR4122_SIU_ADDR
208 #define VRIP_HSP_ADDR VR4122_HSP_ADDR
209 #define VRIP_FIR_ADDR VR4122_FIR_ADDR
210 #define VRIP_MEMCON_ADDR VR4122_MEMCON_ADDR /* XXX: no register */
211 #define VRIP_ISABRG_ADDR VR4122_ISABRG_ADDR /* XXX: no register */
212 #define VRIP_ECU_ADDR VR4122_ECU_ADDR /* XXX: no register */
213 #define VRIP_DCU81_ADDR VR4122_DCU81_ADDR /* XXX: no register */
214 #define VRIP_CSI81_ADDR VR4122_CSI81_ADDR /* XXX: no register */
215 #define VRIP_GIU81_ADDR VR4122_CSI81_ADDR /* XXX: no register */
216 #define VRIP_SIU1_ADDR VR4122_SIU1_ADDR /* XXX: no register */
217 #define VRIP_SCU_ARR VR4122_SCU_ARR /* XXX: no register */
218 #define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR /* XXX: no register */
219 #define VRIP_PCI_ADDR VR4122_PCI_ADDR /* XXX: no register */
220 #define VRIP_PCICONF_ADDR VR4122_PCICONF_ADDR /* XXX: no register */
221 #define VRIP_CSI_ADDR VR4122_CSI_ADDR /* XXX: no register */
222
223 #endif /* VRGROUP_4122_4131 */
224
225 #if defined VRGROUP_4102_4121
226 #define VRIP_BASE_ADDR 0x0b000000
227
228 #define VRIP_BCU_ADDR VR4102_BCU_ADDR
229 #define VRIP_DMAAU_ADDR VR4102_DMAAU_ADDR
230 #define VRIP_DCU_ADDR VR4102_DCU_ADDR
231 #define VRIP_CMU_ADDR VR4102_CMU_ADDR
232 #define VRIP_ICU_ADDR VR4102_ICU_ADDR
233 #define VRIP_PMU_ADDR VR4102_PMU_ADDR
234 #define VRIP_RTC_ADDR VR4102_RTC_ADDR
235 #define VRIP_DSU_ADDR VR4102_DSU_ADDR
236 #define VRIP_GIU_ADDR VR4102_GIU_ADDR
237 #define VRIP_PIU_ADDR VR4102_PIU_ADDR
238 #define VRIP_AIU_ADDR VR4102_AIU_ADDR
239 #define VRIP_KIU_ADDR VR4102_KIU_ADDR
240 #define VRIP_DSIU_ADDR VR4102_DSIU_ADDR
241 #define VRIP_LED_ADDR VR4102_LED_ADDR
242 #define VRIP_SIU_ADDR VR4102_SIU_ADDR
243 #define VRIP_HSP_ADDR VR4102_HSP_ADDR
244 #define VRIP_FIR_ADDR VR4102_FIR_ADDR
245 #define VRIP_MEMCON_ADDR VR4102_MEMCON_ADDR /* XXX: no register */
246 #define VRIP_ISABRG_ADDR VR4102_ISABRG_ADDR /* XXX: no register */
247 #define VRIP_ECU_ADDR VR4102_ECU_ADDR /* XXX: no register */
248 #define VRIP_DCU81_ADDR VR4102_DCU81_ADDR /* XXX: no register */
249 #define VRIP_CSI81_ADDR VR4102_CSI81_ADDR /* XXX: no register */
250 #define VRIP_GIU81_ADDR VR4102_GIU81_ADDR /* XXX: no register */
251 #define VRIP_SIU1_ADDR VR4102_SIU1_ADDR /* XXX: no register */
252 #define VRIP_SCU_ARR VR4102_SCU_ARR /* XXX: no register */
253 #define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR /* XXX: no register */
254 #define VRIP_PCI_ADDR VR4102_PCI_ADDR /* XXX: no register */
255 #define VRIP_PCICONF_ADDR VR4102_PCICONF_ADDR /* XXX: no register */
256 #define VRIP_CSI_ADDR VR4102_CSI_ADDR /* XXX: no register */
257
258 #endif /* VRGROUP_4102_4121 */
259
260 #endif /* SINGLE_VRIP_BASE */
261
262 /*
263 * ICU interrupt level
264 */
265 /* reserved 62-31 */
266 #define VRIP_INTR_BCU 25
267 #define VRIP_INTR_CSI 24
268 #define VRIP_INTR_SCU 23
269 #define VRIP_INTR_PCI 22
270 #define VRIP_INTR_LCD 22 /* 4181 */
271 #define VRIP_INTR_DSIU 21
272 #define VRIP_INTR_DCU81 21 /* 4181 */
273 #define VRIP_INTR_FIR 20
274 #define VRIP_INTR_TCLK 19
275 #define VRIP_INTR_CSI81 19 /* 4181 */
276 #define VRIP_INTR_HSP 18
277 #define VRIP_INTR_ECU 18 /* 4181 */
278 #define VRIP_INTR_LED 17
279 #define VRIP_INTR_RTCL2 16
280 /* reserved 15,14 */
281 #define VRIP_INTR_DOZEPIU 13
282 #define VRIP_INTR_CLKRUN 12
283 #define VRIP_INTR_SOFT 11
284 #define VRIP_INTR_WRBERR 10
285 #define VRIP_INTR_SIU 9
286 #define VRIP_INTR_GIU 8
287 #define VRIP_INTR_KIU 7
288 #define VRIP_INTR_AIU 6
289 #define VRIP_INTR_PIU 5
290 /* reserved 4 VRC4171 use this ??? */
291 #define VRIP_INTR_ETIMER 3
292 #define VRIP_INTR_RTCL1 2
293 #define VRIP_INTR_POWER 1
294 #define VRIP_INTR_BAT 0
295
296 #endif /* VRIPREG_H */
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