/[gxemul]/trunk/src/include/vr_rtcreg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/vr_rtcreg.h

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6404 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /* GXemul: $Id: vr_rtcreg.h,v 1.1 2006/10/02 09:26:53 debug Exp $ */
2 /* $NetBSD: rtcreg.h,v 1.8 2002/02/10 14:36:52 sato Exp $ */
3
4 #ifndef VR_RTCREG_H
5 #define VR_RTCREG_H
6
7 /*-
8 * Copyright (c) 1999 Shin Takemura. All rights reserved.
9 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
10 * Copyright (c) 1999 PocketBSD Project. All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the PocketBSD project
23 * and its contributors.
24 * 4. Neither the name of the project nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 */
41
42 #define SECMIN ((unsigned)60) /* seconds per minute */
43 #define SECHOUR ((unsigned)(60*SECMIN)) /* seconds per hour */
44
45 #define SEC2MIN ((unsigned)60/2) /* 2seconds per minute */
46 #define SEC2HOUR ((unsigned)(60*SECMIN)/2) /* 2seconds per hour */
47 #define SEC2DAY ((unsigned)(24*SECHOUR)/2) /* 2seconds per day */
48 #define SEC2YR ((unsigned)(365*SECDAY)/2) /* 2seconds per common year */
49
50 #define YRREF 1999
51 #define MREF 1
52 #define DREF 1
53
54 #ifndef YBASE
55 #define YBASE 1900
56 #endif
57
58 #define EPOCHOFF 0 /* epoch offset */
59 #ifndef EPOCHYEAR
60 #define EPOCHYEAR 1850 /* XXX */ /* WINCE epoch year */
61 #endif
62 #define EPOCHMONTH 1 /* WINCE epoch month of year */
63 #define EPOCHDATE 1 /* WINCE epoch date of month */
64
65 #define LEAPYEAR4(year) ((((year) % 4) == 0 && ((year) % 100) != 0) || ((year%400)) == 0)
66 #define LEAPYEAR2(year) (((year) % 4) == 0)
67
68 /*
69 * RTC (Real Time Clock Unit) Registers definitions.
70 * start 0x0B0000C0 (Vr4102-4121)
71 * start 0x0F000100 (Vr4122-4131)
72 * start 0x0B0000C0 (Vr4181)
73 */
74 #define RTC_NO_REG_W 0xffffffff
75
76 #define ETIME_L_REG_W 0x000 /* Elapsed Time L */
77 #define ETIME_M_REG_W 0x002 /* Elapsed Time M */
78 #define ETIME_H_REG_W 0x004 /* Elapsed Time H */
79
80 #define ETIME_L_HZ 0x8000 /* 1 HZ */
81
82
83 #define ECMP_L_REG_W 0x008 /* Elapsed Compare L */
84 #define ECMP_M_REG_W 0x00a /* Elapsed Compare M */
85 #define ECMP_H_REG_W 0x00c /* Elapsed Compare H */
86
87
88 #define RTCL1_L_REG_W 0x010 /* RTC Long 1 L */
89 #define RTCL1_H_REG_W 0x012 /* RTC Long 1 H */
90
91 #define RTCL1_L_HZ 0x8000 /* 1 HZ */
92
93
94 #define RTCL1_CNT_L_REG_W 0x014 /* RTC Long 1 Count L */
95 #define RTCL1_CNT_H_REG_W 0x016 /* RTC Long 1 Count H */
96
97
98 #define RTCL2_L_REG_W 0x018 /* RTC Long 2 L */
99 #define RTCL2_H_REG_W 0x01a /* RTC Long 2 H */
100
101 #define RTCL2_L_HZ 0x8000 /* 1 HZ */
102
103
104 #define RTCL2_CNT_L_REG_W 0x01c /* RTC Long 2 Count L */
105 #define RTCL2_CNT_H_REG_W 0x01e /* RTC Long 2 Count H */
106
107
108 #define VR4102_TCLK_L_REG_W 0x100 /* TCLK L */
109 #define VR4102_TCLK_H_REG_W 0x102 /* TCLK H */
110 #define VR4122_TCLK_L_REG_W 0x020 /* TCLK L */
111 #define VR4122_TCLK_H_REG_W 0x022 /* TCLK H */
112 #if defined SINGLE_VRIP_BASE
113 #if defined VRGROUP_4102_4121
114 #define TCLK_L_REG_W VR4102_TCLK_L_REG_W /* TCLK L */
115 #define TCLK_H_REG_W VR4102_TCLK_H_REG_W /* TCLK H */
116 #endif /* VRGROUP_4102_4121 */
117 #if defined VRGROUP_4122_4131
118 #define TCLK_L_REG_W VR4122_TCLK_L_REG_W /* TCLK L */
119 #define TCLK_H_REG_W VR4122_TCLK_H_REG_W /* TCLK H */
120 #endif /* VRGROUP_4122_4131 */
121 #if defined VRGROUP_4181
122 #define TCLK_L_REG_W RTC_NO_REG_W
123 #define TCLK_H_REG_W RTC_NO_REG_W
124 #endif /* VRGROUP_4181 */
125 #endif /* defined SINGLE_VRIP_BASE */
126
127
128 #define VR4102_TCLK_CNT_L_REG_W 0x104 /* TCLK Count L */
129 #define VR4102_TCLK_CNT_H_REG_W 0x106 /* TCLK Count H */
130 #define VR4122_TCLK_CNT_L_REG_W 0x024 /* TCLK Count L */
131 #define VR4122_TCLK_CNT_H_REG_W 0x026 /* TCLK Count H */
132 #if defined SINGLE_VRIP_BASE
133 #if defined VRGROUP_4102_4121
134 #define TCLK_CNT_L_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count L */
135 #define TCLK_CNT_H_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count H */
136 #endif /* VRGROUP_4102_4121 */
137 #if defined VRGROUP_4122_4131
138 #define TCLK_CNT_L_REG_W VR4122_TCLK_CNT_L_REG_W /* TCLK Count L */
139 #define TCLK_CNT_H_REG_W VR4122_TCLK_CNT_H_REG_W /* TCLK Count H */
140 #endif /* VRGROUP_4122_4131 */
141 #if defined VRGROUP_4181
142 #define TCLK_CNT_L_REG_W RTC_NO_REG_W
143 #define TCLK_CNT_H_REG_W RTC_NO_REG_W
144 #endif /* VRGROUP_4181 */
145 #endif /* defined SINGLE_VRIP_BASE */
146
147
148 #define VR4102_RTCINT_REG_W 0x11e /* RTC intr reg. */
149 #define VR4122_RTCINT_REG_W 0x03e /* RTC intr reg. */
150 #define VR4181_RTCINT_REG_W 0x11e /* RTC intr reg. */
151 #if defined SINGLE_VRIP_BASE
152 #if defined VRGROUP_4102_4121
153 #define RTCINT_REG_W VR4102_RTCINT_REG_W /* RTC intr reg. */
154 #endif /* VRGROUP_4102_4121 */
155 #if defined VRGROUP_4122_4131
156 #define RTCINT_REG_W VR4122_RTCINT_REG_W /* RTC intr reg. */
157 #endif /* VRGROUP_4122 */
158 #if defined VRGROUP_4181
159 #define RTCINT_REG_W VR4181_RTCINT_REG_W /* RTC intr reg. */
160 #endif /* VRGROUP_4181 */
161 #endif /* defined SINGLE_VRIP_BASE */
162
163 #define RTCINT_TCLOCK (1<<3) /* TClock */
164 #define RTCINT_RTCLONG2 (1<<2) /* RTC Long 2 */
165 #define RTCINT_RTCLONG1 (1<<1) /* RTC Long 1 */
166 #define RTCINT_ELAPSED (1) /* Elapsed time */
167 #define RTCINT_ALL (RTCINT_TCLOCK|RTCINT_RTCLONG2|RTCINT_RTCLONG1|RTCINT_ELAPSED)
168
169 #endif /* VR_RTCREG_H */

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