/[gxemul]/trunk/src/include/tulipreg.h
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Contents of /trunk/src/include/tulipreg.h

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Revision 18 - (show annotations)
Mon Oct 8 16:19:11 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 59562 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============
1 /* GXemul: $Id: tulipreg.h,v 1.3 2005/10/27 14:01:15 debug Exp $ */
2 /* $NetBSD: tulipreg.h,v 1.31 2005/06/23 23:51:42 rpaulo Exp $ */
3
4 #ifndef __volatile
5 #define __volatile
6 #endif
7
8 /*-
9 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
10 * All rights reserved.
11 *
12 * This code is derived from software contributed to The NetBSD Foundation
13 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
14 * NASA Ames Research Center.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. All advertising materials mentioning features or use of this software
25 * must display the following acknowledgement:
26 * This product includes software developed by the NetBSD
27 * Foundation, Inc. and its contributors.
28 * 4. Neither the name of The NetBSD Foundation nor the names of its
29 * contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
33 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
34 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
35 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
36 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGE.
43 */
44
45 #ifndef _DEV_IC_TULIPREG_H_
46 #define _DEV_IC_TULIPREG_H_
47
48 /*
49 * Register description for the Digital Semiconductor ``Tulip'' (21x4x)
50 * Ethernet controller family, and a variety of clone chips, including:
51 *
52 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC):
53 *
54 * These chips are fairly straight-forward Tulip clones.
55 * The 98713 is a very close 21140A clone. It has GPR
56 * and MII media, and a GPIO facility, and uses the ISV
57 * SROM format (or, at least, should, because of the GPIO
58 * facility). The 98713A has MII, no GPIO facility, and
59 * an internal NWay block. The 98715, 98715A, and 98725
60 * have only GPR media and the NWay block. The 98715,
61 * 98715A, and 98725 support power management.
62 *
63 * The 98715AEC adds 802.3x flow Frame based Flow Control to the
64 * 98715A.
65 *
66 * - Lite-On 82C115 (PNIC II):
67 *
68 * A clone of the Macronix MX98725, with the following differences:
69 *
70 * - Wake-On-LAN support
71 * - 128-bit multicast hash table rather than the
72 * standard 512-bit hash table
73 * - 802.3x flow control
74 *
75 * - Lite-On 82C168, 82C169 (PNIC):
76 *
77 * Pretty close, with only a few minor differences:
78 *
79 * - EEPROM is accessed completely differently.
80 * - MII is accessed completely differently.
81 * - No SIO facility (due to the above two differences).
82 * - GPIO interface is different than the 21140's.
83 * - Boards that lack PHYs use the internal NWay block
84 * and transceiver.
85 *
86 * - Winbond 89C840F
87 *
88 * Less similar, but still roughly compatible (enough so
89 * that the driver can be adapted, at least):
90 *
91 * - Registers lack the pad word between them.
92 * - Instead of a setup frame, there are two station
93 * address registers and two multicast hash table
94 * registers (64-bit multicast hash table).
95 * - Only supported media interface is MII-over-SIO.
96 * - Different OPMODE register bits for various things
97 * (mostly media related).
98 *
99 * - ADMtek AL981
100 *
101 * Another pretty-close clone:
102 *
103 * - Wake-On-LAN support
104 * - Instead of a setup frame, there are two station
105 * address registers and two multicast hash table
106 * registers (64-bit multicast hash table).
107 * - 802.3x flow control
108 * - Only supported media interface is built-in PHY
109 * which is accessed through a set of special registers.
110 * - Not all registers have the pad word between them,
111 * but luckily, there are all AL981-specific registers,
112 * so this is easy to deal with.
113 *
114 * - ADMtek AN983 and AN985
115 *
116 * Similar to the ADMtek AL981, but with a few differences.
117 *
118 * - Xircom X3201-3
119 *
120 * CardBus 21143 clone, with a few differences:
121 *
122 * - No MicroWire SROM; Ethernet address must come
123 * from CIS.
124 * - Transmit buffers must also be 32-bit aligned.
125 * - The BUSMODE_SWR bit is not self-clearing.
126 * - Must include FS|LS in setup packet descriptor.
127 * - SIA is not 21143-like, and all media attachments
128 * are MII-on-SIO.
129 *
130 * - Davicom DM9102 and DM9102A
131 *
132 * Pretty similar to the 21140A, with a few differences:
133 *
134 * - Wake-On-LAN support
135 * - DM9102 has built-in 10/100 PHY on MII interface.
136 * - DM9102A has built-in 10/100 PHY on MII interface,
137 * as well as a HomePNA 1 PHY on an alternate MII
138 * interface (selected by clearing OPMODE_PS).
139 * - The chip has a bug in the transmit DMA logic,
140 * requiring that the packet be comprised of only
141 * one DMA segment.
142 * - The bus interface is buggy, and the BUSMODE register
143 * must be initialized to 0.
144 * - There seems to be an interrupt logic bug, requiring
145 * that interrupts be disabled on the chip during the
146 * interrupt handler.
147 *
148 * - ASIX AX88140
149 *
150 * 21433 clone with a few differences:
151 *
152 * - Specific broadcast bit in the OPMODE register.
153 * - Transmit buffer must be 32-bit aligned.
154 * - The BUSMODE_SWR bit is not self-clearing.
155 * - External 10BaseT PHY or 10/100 MII.
156 *
157 * Some of the clone chips have different registers, and some have
158 * different bits in the same registers. These will be denoted by
159 * PMAC, PNICII, PNIC, DM, WINB, ADM and AX in the register/bit names.
160 */
161
162 /*
163 * Tulip buffer descriptor. Must be 4-byte aligned.
164 *
165 * Note for receive descriptors, the byte count fields must
166 * be a multiple of 4.
167 */
168 struct tulip_desc {
169 __volatile u_int32_t td_status; /* Status */
170 __volatile u_int32_t td_ctl; /* Control and Byte Counts */
171 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */
172 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */
173 };
174
175 /*
176 * Descriptor Status bits common to transmit and receive.
177 */
178 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */
179 #define TDSTAT_ES 0x00008000 /* Error Summary */
180
181 /*
182 * Descriptor Status bits for Receive Descriptor.
183 */
184 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */
185 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */
186 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */
187 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */
188 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */
189 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */
190 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */
191 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */
192 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */
193 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */
194 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */
195 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */
196 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */
197 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */
198 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */
199 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */
200 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */
201
202 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16)
203
204 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */
205 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */
206 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */
207 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */
208
209 /*
210 * Descriptor Status bits for Transmit Descriptor.
211 */
212 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */
213 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */
214 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */
215 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */
216 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */
217 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */
218 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */
219 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */
220 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */
221 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */
222 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */
223
224 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3)
225
226 /*
227 * Descriptor Control bits common to transmit and receive.
228 */
229 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */
230 #define TDCTL_SIZE1_SHIFT 0
231
232 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */
233 #define TDCTL_SIZE2_SHIFT 11
234
235 #define TDCTL_ER 0x02000000 /* End of Ring */
236 #define TDCTL_CH 0x01000000 /* Second Address Chained */
237
238 /*
239 * Descriptor Control bits for Transmit Descriptor.
240 */
241 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */
242 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */
243 #define TDCTL_Tx_FS 0x20000000 /* First Segment */
244 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */
245 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */
246 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */
247 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */
248 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */
249
250 /*
251 * The Tulip filter is programmed by "transmitting" a Setup Packet
252 * (indicated by TDCTL_Tx_SET). The filtering type is indicated
253 * as follows:
254 *
255 * FT1 FT0 Description
256 * --- --- -----------
257 * 0 0 Perfect Filtering: The Tulip interprets the
258 * descriptor buffer as a table of 16 MAC addresses
259 * that the Tulip should receive.
260 *
261 * 0 1 Hash Filtering: The Tulip interprets the
262 * descriptor buffer as a 512-bit hash table
263 * plus one perfect address. If the incoming
264 * address is Multicast, the hash table filters
265 * the address, else the address is filtered by
266 * the perfect address.
267 *
268 * 1 0 Inverse Filtering: Like Perfect Filtering, except
269 * the table is addresses that the Tulip does NOT
270 * receive.
271 *
272 * 1 1 Hash-only Filtering: Like Hash Filtering, but
273 * physical addresses are matched by the hash table
274 * as well, and not by matching a single perfect
275 * address.
276 *
277 * A Setup Packet must always be 192 bytes long. The Tulip can store
278 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering
279 * or Inverse Filtering mode, then unused entries should duplicate
280 * one of the valid entries.
281 */
282 #define TDCTL_Tx_FT_PERFECT 0
283 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0
284 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1
285 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0)
286
287 #define TULIP_SETUP_PACKET_LEN 192
288 #define TULIP_MAXADDRS 16
289 #define TULIP_MCHASHSIZE 512
290 #define TULIP_PNICII_HASHSIZE 128
291
292 /*
293 * Maximum size of a Tulip Ethernet Address ROM or SROM.
294 */
295 #define TULIP_ROM_SIZE(bits) (2 << (bits))
296 #define TULIP_MAX_ROM_SIZE 512
297
298 /*
299 * Format of the standard Tulip SROM information:
300 *
301 * Byte offset Size Usage
302 * 0 18 reserved
303 * 18 1 SROM Format Version
304 * 19 1 Chip Count
305 * 20 6 IEEE Network Address
306 * 26 1 Chip 0 Device Number
307 * 27 2 Chip 0 Info Leaf Offset
308 * 29 1 Chip 1 Device Number
309 * 30 2 Chip 1 Info Leaf Offset
310 * 32 1 Chip 2 Device Number
311 * 33 2 Chip 2 Info Leaf Offset
312 * ... 1 Chip n Device Number
313 * ... 2 Chip n Info Leaf Offset
314 * ... ... ...
315 * Chip Info Leaf Information
316 * ...
317 * ...
318 * ...
319 * 126 2 CRC32 checksum
320 */
321 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */
322 #define TULIP_ROM_CHIP_COUNT 19 /* B */
323 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20
324 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */
325 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */
326 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */
327 #define TULIP_ROM_CRC32_CHECKSUM1 94 /* W */
328
329 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */
330 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */
331 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3
332
333 #define SELECT_CONN_TYPE_TP 0x0000
334 #define SELECT_CONN_TYPE_BNC 0x0001
335 #define SELECT_CONN_TYPE_AUI 0x0002
336 #define SELECT_CONN_TYPE_100TX 0x0003
337 #define SELECT_CONN_TYPE_100T4 0x0006
338 #define SELECT_CONN_TYPE_100FX 0x0007
339 #define SELECT_CONN_TYPE MII_10T 0x0009
340 #define SELECT_CONN_TYPE_MII_100TX 0x000d
341 #define SELECT_CONN_TYPE_MII_100T4 0x000f
342 #define SELECT_CONN_TYPE_MII_100FX 0x0010
343 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100
344 #define SELECT_CONN_TYPE_TP_FDX 0x0204
345 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a
346 #define SELECT_CONN_TYPE_100TX_FDX 0x020e
347 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211
348 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400
349 #define SELECT_CONN_TYPE_ASENSE 0x0800
350 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800
351 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900
352
353 #define TULIP_ROM_MB_MEDIA_CODE 0x3f
354 #define TULIP_ROM_MB_MEDIA_TP 0x00
355 #define TULIP_ROM_MB_MEDIA_BNC 0x01
356 #define TULIP_ROM_MB_MEDIA_AUI 0x02
357 #define TULIP_ROM_MB_MEDIA_100TX 0x03
358 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04
359 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05
360 #define TULIP_ROM_MB_MEDIA_100T4 0x06
361 #define TULIP_ROM_MB_MEDIA_100FX 0x07
362 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08
363
364 #define TULIP_ROM_MB_EXT 0x40
365
366 #define TULIP_ROM_MB_CSR13 1 /* W */
367 #define TULIP_ROM_MB_CSR14 3 /* W */
368 #define TULIP_ROM_MB_CSR15 5 /* W */
369
370 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1)
371
372 #define TULIP_ROM_MB_NOINDICATOR 0x8000
373 #define TULIP_ROM_MB_DEFAULT 0x4000
374 #define TULIP_ROM_MB_POLARITY 0x0080
375 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18)
376 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1))
377
378 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */
379 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */
380 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */
381 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */
382 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */
383 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */
384
385 #define TULIP_ROM_GETW(data, off) ((uint32_t)(data)[(off)] | \
386 (uint32_t)((data)[(off) + 1]) << 8)
387
388 /*
389 * Tulip control registers.
390 */
391
392 #define TULIP_CSR0 0x00
393 #define TULIP_CSR1 0x08
394 #define TULIP_CSR2 0x10
395 #define TULIP_CSR3 0x18
396 #define TULIP_CSR4 0x20
397 #define TULIP_CSR5 0x28
398 #define TULIP_CSR6 0x30
399 #define TULIP_CSR7 0x38
400 #define TULIP_CSR8 0x40
401 #define TULIP_CSR9 0x48
402 #define TULIP_CSR10 0x50
403 #define TULIP_CSR11 0x58
404 #define TULIP_CSR12 0x60
405 #define TULIP_CSR13 0x68
406 #define TULIP_CSR14 0x70
407 #define TULIP_CSR15 0x78
408 #define TULIP_CSR16 0x80
409 #define TULIP_CSR17 0x88
410 #define TULIP_CSR18 0x90
411 #define TULIP_CSR19 0x98
412 #define TULIP_CSR20 0xa0
413 #define TULIP_CSR21 0xa8
414 #define TULIP_CSR22 0xb0
415 #define TULIP_CSR23 0xb8
416 #define TULIP_CSR24 0xc0
417 #define TULIP_CSR25 0xc8
418 #define TULIP_CSR26 0xd0
419 #define TULIP_CSR27 0xd8
420 #define TULIP_CSR28 0xe0
421 #define TULIP_CSR29 0xe8
422 #define TULIP_CSR30 0xf0
423 #define TULIP_CSR31 0xf8
424
425 #define TULIP_CSR_INDEX(csr) ((csr) >> 3)
426
427 /* CSR0 - Bus Mode */
428 #define CSR_BUSMODE TULIP_CSR0
429 #define BUSMODE_SWR 0x00000001 /* software reset */
430 #define BUSMODE_BAR 0x00000002 /* bus arbitration */
431 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */
432 #define BUSMODE_BLE 0x00000080 /* big endian */
433 /* programmable burst length */
434 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */
435 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */
436 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */
437 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */
438 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */
439 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */
440 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */
441 /* cache alignment */
442 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */
443 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */
444 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */
445 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */
446 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */
447 /* must be zero on most */
448 /* transmit auto-poll */
449 /*
450 * Transmit auto-polling not supported on:
451 * Winbond 89C040F
452 * Xircom X3201-3
453 * Davicom DM9102 (buggy BUSMODE register)
454 * ASIX AX88140
455 */
456 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */
457 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */
458 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */
459 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */
460 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */
461 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */
462 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */
463 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */
464 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */
465 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */
466 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */
467 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */
468 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */
469 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */
470 /* on Lite-On PNIC */
471
472
473 /* CSR1 - Transmit Poll Demand */
474 #define CSR_TXPOLL TULIP_CSR1
475 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */
476
477
478 /* CSR2 - Receive Poll Demand */
479 #define CSR_RXPOLL TULIP_CSR2
480 #define RXPOLL_RPD 0x00000001 /* receive poll demand */
481
482
483 /* CSR3 - Receive List Base Address */
484 #define CSR_RXLIST TULIP_CSR3
485
486 /* CSR4 - Transmit List Base Address */
487 #define CSR_TXLIST TULIP_CSR4
488
489 /* CSR5 - Status */
490 #define CSR_STATUS TULIP_CSR5
491 #define STATUS_TI 0x00000001 /* transmit interrupt */
492 #define STATUS_TPS 0x00000002 /* transmit process stopped */
493 #define STATUS_TU 0x00000004 /* transmit buffer unavail */
494 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */
495 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */
496 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */
497 #define STATUS_WINB_RERR 0x00000010 /* receive error */
498 #define STATUS_UNF 0x00000020 /* transmit underflow */
499 #define STATUS_RI 0x00000040 /* receive interrupt */
500 #define STATUS_RU 0x00000080 /* receive buffer unavail */
501 #define STATUS_RPS 0x00000100 /* receive process stopped */
502 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */
503 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed
504 (21040) */
505 #define STATUS_ETI 0x00000400 /* early transmit interrupt
506 (21142/PMAC/Winbond) */
507 #define STATUS_FD 0x00000800 /* full duplex short frame
508 received (21040) */
509 #define STATUS_TM 0x00000800 /* timer expired (21041) */
510 #define STATUS_LNF 0x00001000 /* link fail (21040) */
511 #define STATUS_SE 0x00002000 /* system error */
512 #define STATUS_ER 0x00004000 /* early receive (21041) */
513 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */
514 #define STATUS_NIS 0x00010000 /* normal interrupt summary */
515 #define STATUS_RS 0x000e0000 /* receive process state */
516 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */
517 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive
518 descriptor */
519 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end
520 of receive */
521 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */
522 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */
523 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive
524 descriptor */
525 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current
526 frame from FIFO */
527 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current
528 frame from FIFO into
529 buffer */
530 #define STATUS_DM_RS_STOPPED 0x00000000 /* Stopped */
531 #define STATUS_DM_RS_FETCH 0x00020000 /* Running - fetch receive
532 descriptor */
533 #define STATUS_DM_RS_WAIT 0x00040000 /* Running - wait for packet */
534 #define STATUS_DM_RS_QUEUE 0x00060000 /* Running - queue current
535 frame from FIFO into
536 buffer */
537 #define STATUS_DM_RS_CLOSE_OWN 0x00080000 /* Running - close receive
538 descriptor, clear own */
539 #define STATUS_DM_RS_CLOSE_ST 0x000a0000 /* Running - close receive
540 descriptor, write status */
541 #define STATUS_DM_RS_SUSPENDED 0x000c0000 /* Suspended */
542 #define STATUS_DM_RS_FLUSH 0x000e0000 /* Running - flush current
543 frame from FIFO */
544 #define STATUS_TS 0x00700000 /* transmit process state */
545 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */
546 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit
547 descriptor */
548 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end
549 of transmission */
550 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from
551 memory and queue into
552 FIFO */
553 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */
554 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */
555 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */
556 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit
557 descriptor */
558 #define STATUS_DM_TS_STOPPED 0x00000000 /* Stopped */
559 #define STATUS_DM_TS_FETCH 0x00100000 /* Running - fetch transmit
560 descriptor */
561 #define STATUS_DM_TS_SETUP 0x00200000 /* Running - Setup packet */
562 #define STATUS_DM_TS_READING 0x00300000 /* Running - read buffer from
563 memory and queue into
564 FIFO */
565 #define STATUS_DM_TS_CLOSE_OWN 0x00400000 /* Running - close transmit
566 descriptor, clear own */
567 #define STATUS_DM_TS_WAIT 0x00500000 /* Running - wait for end
568 of transmission */
569 #define STATUS_DM_TS_CLOSE_ST 0x00600000 /* Running - close transmit
570 descriptor, write status */
571 #define STATUS_DM_TS_SUSPENDED 0x00700000 /* Suspended */
572 #define STATUS_EB 0x03800000 /* error bits */
573 #define STATUS_EB_PARITY 0x00000000 /* parity errror */
574 #define STATUS_EB_MABT 0x00800000 /* master abort */
575 #define STATUS_EB_TABT 0x01000000 /* target abort */
576 #define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */
577 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */
578 #define STATUS_LC 0x08000000 /* 100baseTX link change
579 (21142/PMAC) */
580 #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */
581 #define STATUS_X3201_PMEIS 0x10000000 /* power management event
582 interrupt summary */
583 #define STATUS_X3201_SFIS 0x80000000 /* second function (Modem)
584 interrupt status */
585
586
587 /* CSR6 - Operation Mode */
588 #define CSR_OPMODE TULIP_CSR6
589 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */
590 #define OPMODE_SR 0x00000002 /* start receive */
591 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */
592 #define OPMODE_PB 0x00000008 /* pass bad frames */
593 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */
594 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */
595 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */
596 #define OPMODE_SB 0x00000020 /* start backoff counter */
597 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */
598 #define OPMODE_PR 0x00000040 /* promiscuous mode */
599 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */
600 #define OPMODE_PM 0x00000080 /* pass all multicast */
601 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */
602 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */
603 #define OPMODE_AX_RB 0x00000100 /* recieve broadcast packets */
604 #define OPMODE_FD 0x00000200 /* full-duplex mode */
605 #define OPMODE_OM 0x00000c00 /* operating mode */
606 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */
607 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */
608 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */
609 #define OPMODE_FC 0x00001000 /* force collision */
610 #define OPMODE_ST 0x00002000 /* start transmitter */
611 #define OPMODE_TR 0x0000c000 /* threshold control */
612 #define OPMODE_TR_72 0x00000000 /* 72 bytes */
613 #define OPMODE_TR_96 0x00004000 /* 96 bytes */
614 #define OPMODE_TR_128 0x00008000 /* 128 bytes */
615 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */
616 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */
617 #define OPMODE_WINB_TTH_SHIFT 14
618 #define OPMODE_BP 0x00010000 /* backpressure enable */
619 #define OPMODE_CA 0x00020000 /* capture effect enable */
620 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */
621 /*
622 * On Davicom DM9102, OPMODE_PS and OPMODE_HBD must
623 * always be set.
624 */
625 #define OPMODE_PS 0x00040000 /* port select:
626 1 = MII/SYM, 0 = SRL
627 (21140) */
628 #define OPMODE_HBD 0x00080000 /* heartbeat disable:
629 set in MII/SYM 100mbps,
630 set according to PHY
631 in MII 10mbps mode
632 (21140) */
633 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */
634 #define OPMODE_SF 0x00200000 /* store and forward mode
635 (21140) */
636 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */
637 #define OPMODE_WINB_REIT_SHIFT 21
638 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode:
639 1 = 10mbps, 0 = 100mbps
640 (21140) */
641 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */
642 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */
643 #define OPMODE_MBO 0x02000000 /* must be one (21140,
644 DM9102) */
645 #define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB
646 (21142) */
647 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx
648 frames (PNIC) */
649 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */
650 #define OPMODE_RA 0x40000000 /* receive all (21140) */
651 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC
652 (PNIC) */
653 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */
654 #define OPMODE_SC 0x80000000 /* special capture effect
655 enable (21041+) */
656 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */
657
658 /* Shorthand for media-related OPMODE bits */
659 #define OPMODE_MEDIA_BITS (OPMODE_FD|OPMODE_PS|OPMODE_TTM|OPMODE_PCS|OPMODE_SCR)
660
661 /* CSR7 - Interrupt Enable */
662 #define CSR_INTEN TULIP_CSR7
663 /* See bits for CSR5 -- Status */
664
665
666 /* CSR8 - Missed Frames */
667 #define CSR_MISSED TULIP_CSR8
668 #define MISSED_MFC 0x0000ffff /* missed packet count */
669 #define MISSED_MFO 0x00010000 /* missed packet count
670 overflowed */
671 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter
672 (21140) */
673 #define MISSED_OCO 0x10000000 /* overflow counter overflowed
674 (21140) */
675
676 #define MISSED_GETMFC(x) ((x) & MISSED_MFC)
677 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17)
678
679
680 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */
681 #define CSR_MIIROM TULIP_CSR9
682 #define MIIROM_DATA 0x000000ff /* byte of data from
683 Ethernet Address ROM
684 (21040), byte of data
685 to/from Boot ROM (21041+) */
686 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */
687 #define MIIROM_SROMSK 0x00000002 /* SROM clock */
688 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */
689 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */
690 #define MIIROM_REG 0x00000400 /* external register select */
691 #define MIIROM_SR 0x00000800 /* SROM select */
692 #define MIIROM_BR 0x00001000 /* boot ROM select */
693 #define MIIROM_WR 0x00002000 /* write to boot ROM */
694 #define MIIROM_RD 0x00004000 /* read from boot ROM */
695 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */
696 #define MIIROM_MDC 0x00010000 /* MII clock */
697 #define MIIROM_MDO 0x00020000 /* MII data out */
698 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode
699 1 = PHY in read,
700 0 = PHY in write */
701 #define MIIROM_MDI 0x00080000 /* MII data in */
702 #define MIIROM_DN 0x80000000 /* data not valid (21040) */
703
704 #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def)
705 1 == LED0 speed */
706 #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def)
707 1 == LED1 link/act */
708 #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def)
709 1 == LED2 collision */
710 #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def)
711 1 == LED3 full duplex */
712
713 /* SROM opcodes */
714 #define TULIP_SROM_OPC_ERASE 0x04
715 #define TULIP_SROM_OPC_WRITE 0x05
716 #define TULIP_SROM_OPC_READ 0x06
717
718 /* The Lite-On PNIC does this completely differently */
719 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */
720 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */
721
722
723 /* CSR10 - Boot ROM address register (21041+). */
724 #define CSR_ROMADDR TULIP_CSR10
725 #define ROMADDR_MASK 0x000003ff /* boot rom address */
726
727
728 /* CSR11 - General Purpose Timer (21041+). */
729 #define CSR_GPT TULIP_CSR11
730 #define GPT_VALUE 0x0000ffff /* timer value */
731 #define GPT_CON 0x00010000 /* continuous mode */
732 /* 21143-PD and 21143-TD Interrupt Mitigation bits */
733 #define GPT_NRX 0x000e0000 /* number of Rx packets */
734 #define GPT_RXT 0x00f00000 /* Rx timer */
735 #define GPT_NTX 0x07000000 /* number of Tx packets */
736 #define GPT_TXT 0x78000000 /* Tx timer */
737 #define GPT_CYCLE 0x80000000 /* cycle size */
738
739
740 /* CSR12 - SIA Status Register. */
741 #define CSR_SIASTAT TULIP_CSR12
742 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication
743 (21040) */
744 #define SIASTAT_MRA 0x00000001 /* MII receive activity
745 (21142) */
746 #define SIASTAT_NCR 0x00000002 /* network connection error */
747 #define SIASTAT_LS100 0x00000002 /* 100baseT link status
748 0 == pass (21142) */
749 #define SIASTAT_LKF 0x00000004 /* link fail status */
750 #define SIASTAT_LS10 0x00000004 /* 10baseT link status
751 0 == pass (21142) */
752 #define SIASTAT_APS 0x00000008 /* auto polarity status */
753 #define SIASTAT_DSD 0x00000010 /* PLL self test done */
754 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */
755 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */
756 #define SIASTAT_DAO 0x00000080 /* PLL all one */
757 #define SIASTAT_SRA 0x00000100 /* selected port receive
758 activity (21041) */
759 #define SIASTAT_ARA 0x00000100 /* AUI receive activity
760 (21142) */
761 #define SIASTAT_NRA 0x00000200 /* non-selected port
762 receive activity (21041) */
763 #define SIASTAT_TRA 0x00000200 /* 10base-T receive activity
764 (21142) */
765 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected
766 (21041) */
767 #define SIASTAT_TRF 0x00000800 /* transmit remote fault
768 (21041) */
769 #define SIASTAT_ANS 0x00007000 /* autonegotiation state
770 (21041) */
771 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */
772 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */
773 #define SIASTAT_ANS_START 0x00001000 /* (MX98715AEC) */
774 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */
775 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */
776 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */
777 #define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */
778 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */
779 #define SIASTAT_LPN 0x00008000 /* link partner negotiable
780 (21041) */
781 #define SIASTAT_LPC 0xffff0000 /* link partner code word */
782
783 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16)
784
785
786 /* CSR13 - SIA Connectivity Register. */
787 #define CSR_SIACONN TULIP_CSR13
788 #define SIACONN_SRL 0x00000001 /* SIA reset
789 (0 == reset) */
790 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection
791 (21040) */
792 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */
793 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */
794 #define SIACONN_EDP 0x00000010 /* SIA PLL external input
795 enable (21040) */
796 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer
797 (21040) */
798 #define SIACONN_SIM 0x00000040 /* serial interface input
799 multiplexer (21040) */
800 #define SIACONN_ASE 0x00000080 /* APLL start enable
801 (21040) */
802 #define SIACONN_SEL 0x00000f00 /* external port output
803 multiplexer select
804 (21040) */
805 #define SIACONN_IE 0x00001000 /* input enable (21040) */
806 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3
807 (21040) */
808 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4
809 (21040) */
810 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7
811 (21040) */
812 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode;
813 always set to this value
814 for normal operation
815 (21041) */
816
817
818 /* CSR14 - SIA Transmit Receive Register. */
819 #define CSR_SIATXRX TULIP_CSR14
820 #define SIATXRX_ECEN 0x00000001 /* encoder enable */
821 #define SIATXRX_LBK 0x00000002 /* loopback enable */
822 #define SIATXRX_DREN 0x00000004 /* driver enable */
823 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */
824 #define SIATXRX_CPEN 0x00000030 /* compensation enable */
825 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */
826 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */
827 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */
828 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */
829 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */
830 #define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */
831 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable
832 (21041/21142) */
833 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */
834 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */
835 #define SIATXRX_CLD 0x00000400 /* collision detect enable */
836 #define SIATXRX_SQE 0x00000800 /* signal quality generation
837 enable */
838 #define SIATXRX_LTE 0x00001000 /* link test enable */
839 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */
840 #define SIATXRX_SPP 0x00004000 /* set polarity plus */
841 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing
842 enable (21041/21142) */
843 #define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */
844 #define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */
845 #define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */
846
847
848 /* CSR15 - SIA General Register. */
849 #define CSR_SIAGEN TULIP_CSR15
850 #define SIAGEN_JBD 0x00000001 /* jabber disable */
851 #define SIAGEN_HUJ 0x00000002 /* host unjab */
852 #define SIAGEN_JCK 0x00000004 /* jabber clock */
853 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */
854 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */
855 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */
856 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */
857 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */
858 #define SIAGEN_TSCK 0x00000100 /* test clock */
859 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */
860 #define SIAGEN_FLF 0x00000400 /* force link fail */
861 #define SIAGEN_LSD 0x00000800 /* LED stretch disable
862 (21041) */
863 #define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */
864 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */
865 #define SIAGEN_FRL 0x00002000 /* force receiver low */
866 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */
867 #define SIAGEN_RMP 0x00004000 /* received magic packet
868 (21143) */
869 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */
870 #define SIAGEN_HCKR 0x00008000 /* hacker (21143) */
871 #define SIAGEN_MD 0x000f0000 /* general purpose mode/data */
872 #define SIAGEN_LGS0 0x00100000 /* LED/GEP 0 select */
873 #define SIAGEN_LGS1 0x00200000 /* LED/GEP 1 select */
874 #define SIAGEN_LGS2 0x00400000 /* LED/GEP 2 select */
875 #define SIAGEN_LGS3 0x00800000 /* LED/GEP 3 select */
876 #define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */
877 #define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */
878 #define SIAGEN_RME 0x04000000 /* receive match enable */
879 #define SIAGEN_CWE 0x08000000 /* control write enable */
880 #define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */
881 #define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */
882 #define SIAGEN_RMI 0x40000000 /* receive match interrupt */
883
884
885 /* CSR12 - General Purpose Port (21140+). */
886 #define CSR_GPP TULIP_CSR12
887 #define GPP_MD 0x000000ff /* general purpose mode/data */
888 #define GPP_GPC 0x00000100 /* general purpose control */
889 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */
890 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */
891
892 #define GPP_PNIC_IN(x) (1 << (x))
893 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4)))
894
895 /*
896 * The Lite-On PNIC manual recommends the following for the General Purpose
897 * I/O pins:
898 *
899 * 0 Speed Relay 1 == 100mbps
900 * 1 100mbps loopback 1 == loopback
901 * 2 BNC DC-DC converter 1 == select BNC
902 * 3 Link 100 1 == 100baseTX link status
903 */
904 #define GPP_PNIC_PIN_SPEED_RLY 0
905 #define GPP_PNIC_PIN_100M_LPKB 1
906 #define GPP_PNIC_PIN_BNC_XMER 2
907 #define GPP_PNIC_PIN_LNK100X 3
908
909 /*
910 * Definitions used for the SMC 9332DST (21140) board.
911 */
912 #define GPP_SMC9332DST_PINS 0x3f /* General Purpose Pin directions */
913 #define GPP_SMC9332DST_OK10 0x80 /* 10 Mb/sec Signal Detect gep<7> */
914 #define GPP_SMC9332DST_OK100 0x40 /* 100 Mb/sec Signal Detect gep<6> */
915 #define GPP_SMC9332DST_INIT 0x09 /* No loopback --- point-to-point */
916
917 /*
918 * Definitions used for the Cogent EM1x0 (21140) board.
919 */
920 #define GPP_COGENT_EM1x0_PINS 0x3f /* General Purpose Pin directions */
921 #define GPP_COGENT_EM1x0_INIT 0x09 /* No loopback --- point-to-point */
922
923
924 /*
925 * Digital Semiconductor 21040 registers.
926 */
927
928 /* CSR11 - Full Duplex Register */
929 #define CSR_21040_FDX TULIP_CSR11
930 #define FDX21040_FDXACV 0x0000ffff /* full duplex
931 autoconfiguration value */
932
933
934 /* SIA configuration for 10base-T (from the 21040 manual) */
935 #define SIACONN_21040_10BASET 0x0000ef01
936 #define SIATXRX_21040_10BASET 0x0000ffff
937 #define SIAGEN_21040_10BASET 0x00000000
938
939
940 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */
941 #define SIACONN_21040_10BASET_FDX 0x0000ef01
942 #define SIATXRX_21040_10BASET_FDX 0x0000fffd
943 #define SIAGEN_21040_10BASET_FDX 0x00000000
944
945
946 /* SIA configuration for 10base-5 (from the 21040 manual) */
947 #define SIACONN_21040_AUI 0x0000ef09
948 #define SIATXRX_21040_AUI 0x00000705
949 #define SIAGEN_21040_AUI 0x00000006
950
951
952 /* SIA configuration for External SIA (from the 21040 manual) */
953 #define SIACONN_21040_EXTSIA 0x00003041
954 #define SIATXRX_21040_EXTSIA 0x00000000
955 #define SIAGEN_21040_EXTSIA 0x00000006
956
957
958 /*
959 * Digital Semiconductor 21041 registers.
960 */
961
962 /* SIA configuration for 10base-T (from the 21041 manual) */
963 #define SIACONN_21041_10BASET 0x0000ef01
964 #define SIATXRX_21041_10BASET 0x0000ff3f
965 #define SIAGEN_21041_10BASET 0x00000000
966
967 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET
968 #define SIATXRX_21041P2_10BASET 0x0000ffff
969 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET
970
971
972 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */
973 #define SIACONN_21041_10BASET_FDX 0x0000ef01
974 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d
975 #define SIAGEN_21041_10BASET_FDX 0x00000000
976
977 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX
978 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff
979 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX
980
981
982 /* SIA configuration for 10base-5 (from the 21041 manual) */
983 #define SIACONN_21041_AUI 0x0000ef09
984 #define SIATXRX_21041_AUI 0x0000f73d
985 #define SIAGEN_21041_AUI 0x0000000e
986
987 #define SIACONN_21041P2_AUI SIACONN_21041_AUI
988 #define SIATXRX_21041P2_AUI 0x0000f7fd
989 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI
990
991
992 /* SIA configuration for 10base-2 (from the 21041 manual) */
993 #define SIACONN_21041_BNC 0x0000ef09
994 #define SIATXRX_21041_BNC 0x0000f73d
995 #define SIAGEN_21041_BNC 0x00000006
996
997 #define SIACONN_21041P2_BNC SIACONN_21041_BNC
998 #define SIATXRX_21041P2_BNC 0x0000f7fd
999 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC
1000
1001
1002 /*
1003 * Digital Semiconductor 21142/21143 registers.
1004 */
1005
1006 /* SIA configuration for 10baseT (from the 21143 manual) */
1007 #define SIACONN_21142_10BASET 0x00000001
1008 #define SIATXRX_21142_10BASET 0x00007f3f
1009 #define SIAGEN_21142_10BASET 0x00000008
1010
1011
1012 /* SIA configuration for 10baseT full-duplex (from the 21143 manual) */
1013 #define SIACONN_21142_10BASET_FDX 0x00000001
1014 #define SIATXRX_21142_10BASET_FDX 0x00007f3d
1015 #define SIAGEN_21142_10BASET_FDX 0x00000008
1016
1017
1018 /* SIA configuration for 10base5 (from the 21143 manual) */
1019 #define SIACONN_21142_AUI 0x00000009
1020 #define SIATXRX_21142_AUI 0x00004705
1021 #define SIAGEN_21142_AUI 0x0000000e
1022
1023
1024 /* SIA configuration for 10base2 (from the 21143 manual) */
1025 #define SIACONN_21142_BNC 0x00000009
1026 #define SIATXRX_21142_BNC 0x00004705
1027 #define SIAGEN_21142_BNC 0x00000006
1028
1029
1030 /*
1031 * Lite-On 82C168/82C169 registers.
1032 */
1033
1034 /* ENDEC General Register */
1035 #define CSR_PNIC_ENDEC 0x78
1036 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */
1037
1038 /* SROM Power Register */
1039 #define CSR_PNIC_SROMPWR 0x90
1040 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */
1041 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment
1042 burst type; 1 == burst to
1043 boundary, 0 == single-cycle
1044 to boundary */
1045
1046 /* SROM Control Register */
1047 #define CSR_PNIC_SROMCTL 0x98
1048 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */
1049 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */
1050 #define PNIC_SROMCTL_READ 0x00000600 /* read command */
1051
1052 /* MII Access Register */
1053 #define CSR_PNIC_MII 0xa0
1054 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */
1055 #define PNIC_MII_REG 0x007c0000 /* register mask */
1056 #define PNIC_MII_REGSHIFT 18
1057 #define PNIC_MII_PHY 0x0f800000 /* phy mask */
1058 #define PNIC_MII_PHYSHIFT 23
1059 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */
1060 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero;
1061 2 bits are described here */
1062 #define PNIC_MII_MBO 0x40000000 /* must be one */
1063 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */
1064
1065 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */
1066 #define PNIC_MII_READ 0x20000000 /* read PHY command */
1067
1068 /* NWAY Register */
1069 #define CSR_PNIC_NWAY 0xb8
1070 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */
1071 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */
1072 #define PNIC_NWAY_BX 0x00000004 /* bypass transceiver */
1073 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */
1074 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */
1075 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */
1076 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */
1077 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input
1078 voltage */
1079 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */
1080 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity
1081 test */
1082 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */
1083 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */
1084 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */
1085 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */
1086 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */
1087 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */
1088 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */
1089 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */
1090 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */
1091 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */
1092 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */
1093 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */
1094 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */
1095 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */
1096 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */
1097 #define PNIC_NWAY_LPAR_MASK 0xf8000000
1098
1099
1100 /*
1101 * Macronix 98713, 98713A, 98715, 98715A, 98715AEC, 98725, and
1102 * Lite-On 82C115 registers.
1103 */
1104
1105 /*
1106 * Note, the MX98713 is very Tulip-like:
1107 *
1108 * CSR12 General Purpose Port (like 21140)
1109 * CSR13 reserved
1110 * CSR14 reserved
1111 * CSR15 Watchdog Timer (like 21140)
1112 *
1113 * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only
1114 * on the MX98713A and higher.
1115 */
1116
1117 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */
1118 /* See SIASTAT 21142/21143 bits */
1119 #define CSR_PMAC_10TSTAT TULIP_CSR12
1120 #define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \
1121 SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \
1122 SIASTAT_LPN|SIASTAT_LPC)
1123
1124
1125 /* CSR13 - NWAY Reset Register */
1126 #define CSR_PMAC_NWAYRESET TULIP_CSR13
1127 /* See SIACONN 21142/21143 bits */
1128 #define PMAC_SIACONN_MASK (SIACONN_SRL)
1129 #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */
1130
1131
1132 /* CSR14 - 10base-T Control Port */
1133 #define CSR_PMAC_10TCTL TULIP_CSR14
1134 /* See SIATXRX 21142/21143 bits */
1135 #define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \
1136 SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \
1137 SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4)
1138
1139
1140 /* CSR15 - Watchdog Timer Register */
1141 /* MX98713: see 21140 CSR15 */
1142 /* others: see SIAGEN 21142/21143 bits */
1143 #define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \
1144 SIAGEN_RWD|SIAGEN_RWR)
1145
1146
1147 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */
1148 #define CSR_PMAC_TOR TULIP_CSR16
1149 #define PMAC_TOR_98713 0x0F370000
1150 #define PMAC_TOR_98715 0x0B3C0000
1151
1152
1153 /* CSR20 - NWAY Status */
1154 #define CSR_PMAC_NWAYSTAT TULIP_CSR20
1155 /*
1156 * Note: the MX98715A manual claims that EQTEST and PCITEST
1157 * must be set to 1 by software for normal operation, but
1158 * this does not appear to be necessary. This is probably
1159 * one of the things that frobbing the Test Operation Register
1160 * does.
1161 *
1162 * MX98715AEC uses this register for Auto Compensation.
1163 * CSR20<14> and CSR20<9> are called DS130 and DS120
1164 */
1165 #define PMAC_NWAYSTAT_DS120 0x00000200 /* Auto-compensation circ */
1166 #define PMAC_NWAYSTAT_DS130 0x00004000 /* Auto-compensation circ */
1167 #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */
1168 #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */
1169 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */
1170 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */
1171 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */
1172 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */
1173 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */
1174
1175
1176 /* CSR21 - Flow Control Register */
1177 #define CSR_PNICII_FLOWCTL TULIP_CSR21
1178 #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame
1179 catenation feature */
1180 #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result
1181 from NWay */
1182 #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */
1183 #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */
1184 #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */
1185 #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */
1186 #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when
1187 RU interrupt occurs */
1188 #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */
1189 #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */
1190 #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */
1191 #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */
1192 #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */
1193 #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow
1194 control frame */
1195
1196 #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1)
1197 #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1)
1198 #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0)
1199 #define PNICII_FLOWCTL_TH_OVFLW (0)
1200
1201
1202 /* CSR22 - MAC ID Byte 3-0 Register */
1203 #define CSR_PNICII_MACID0 TULIP_CSR22
1204 #define PNICII_MACID_1 0 /* shift */
1205 #define PNICII_MACID_0 8 /* shift */
1206 #define PNICII_MACID_3 16 /* shift */
1207 #define PNICII_MACID_2 24 /* shift */
1208
1209
1210 /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */
1211 #define PNICII_MACID_5 0 /* shift */
1212 #define PNICII_MACID_4 8 /* shift */
1213 #define PNICII_MAGID_5 16 /* shift */
1214 #define PNICII_MAGIC_4 24 /* shift */
1215
1216
1217 /* CSR24 - Magic ID Byte 3-0 Register */
1218 #define PNICII_MAGID_1 0 /* shift */
1219 #define PNICII_MAGID_0 8 /* shift */
1220 #define PNICII_MAGID_3 16 /* shift */
1221 #define PNICII_MAGID_2 24 /* shift */
1222
1223
1224 /* CSR25 - CSR28 - Filter Byte Mask Registers */
1225 #define CSR_PNICII_MASK0 TULIP_CSR25
1226
1227 #define CSR_PNICII_MASK1 TULIP_CSR26
1228
1229 #define CSR_PNICII_MASK2 TULIP_CSR27
1230
1231 #define CSR_PNICII_MASK3 TULIP_CSR28
1232
1233
1234 /* CSR29 - Filter Offset Register */
1235 #define CSR_PNICII_FILOFF TULIP_CSR29
1236 #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */
1237 #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */
1238 #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */
1239 #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */
1240 #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */
1241 #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */
1242 #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */
1243 #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */
1244
1245
1246 /* CSR30 - Filter 1 and 0 CRC-16 Register */
1247 #define CSR_PNICII_FIL01 TULIP_CSR30
1248 #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */
1249 #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */
1250
1251
1252 /* CSR31 = Filter 3 and 2 CRC-16 Register */
1253 #define CSR_PNICII_FIL23 TULIP_CSR31
1254 #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */
1255 #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */
1256
1257
1258 /*
1259 * Winbond 89C840F registers.
1260 */
1261
1262 /* CSR12 - Current Receive Descriptor Register */
1263 #define CSR_WINB_CRDAR TULIP_CSR12
1264
1265
1266 /* CSR13 - Current Receive Buffer Register */
1267 #define CSR_WINB_CCRBAR TULIP_CSR13
1268
1269
1270 /* CSR14 - Multicast Address Register 0 */
1271 #define CSR_WINB_CMA0 TULIP_CSR14
1272
1273
1274 /* CSR15 - Multicast Address Register 1 */
1275 #define CSR_WINB_CMA1 TULIP_CSR15
1276
1277
1278 /* CSR16 - Physical Address Register 0 */
1279 #define CSR_WINB_CPA0 TULIP_CSR16
1280
1281
1282 /* CSR17 - Physical Address Register 1 */
1283 #define CSR_WINB_CPA1 TULIP_CSR17
1284
1285
1286 /* CSR18 - Boot ROM Size Register */
1287 #define CSR_WINB_CBRCR TULIP_CSR18
1288 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */
1289 /* 0x00000001 also no boot rom */
1290 #define WINB_CBRCR_8K 0x00000002 /* 8k */
1291 #define WINB_CBRCR_16K 0x00000003 /* 16k */
1292 #define WINB_CBRCR_32K 0x00000004 /* 32k */
1293 #define WINB_CBRCR_64K 0x00000005 /* 64k */
1294 #define WINB_CBRCR_128K 0x00000006 /* 128k */
1295 #define WINB_CBRCR_256K 0x00000007
1296
1297
1298 /* CSR19 - Current Transmit Descriptor Register */
1299 #define CSR_WINB_CTDAR TULIP_CSR19
1300
1301
1302 /* CSR20 - Current Transmit Buffer Register */
1303 #define CSR_WINB_CTBAR TULIP_CSR20
1304
1305
1306 /*
1307 * ADMtek AL981 registers
1308 *
1309 * We define these as strict byte offsets into PCI space, since
1310 * not all of them have consistent access rules.
1311 */
1312
1313 /* CSR13 - Wake-up Control/Status Register */
1314 #define CSR_ADM_WCSR 0x68
1315 #define ADM_WCSR_LSC 0x00000001 /* link status changed */
1316 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */
1317 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */
1318 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */
1319 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */
1320 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */
1321 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */
1322 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */
1323 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */
1324 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */
1325 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */
1326 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */
1327 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */
1328 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type:
1329 0 == 0000 initial
1330 1 == ffff initial */
1331
1332
1333 /* CSR14 - Wake-up Pattern Data Register */
1334 #define CSR_ADM_WPDR 0x70
1335
1336 /*
1337 * 25 consecutive longword writes are issued to WPDR to
1338 * program the wake-up pattern filter. The data written
1339 * is as follows:
1340 *
1341 * XXX
1342 */
1343
1344
1345 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */
1346
1347
1348 /* CSR16 - Assistant CSR5 (Status Register 2) */
1349 #define CSR_ADM_ASR 0x80
1350 /* 0 - 14: same as CSR5 */
1351 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */
1352 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */
1353 /* XXX Receive state */
1354 /* XXX Transmit state */
1355 #define ADM_ASR_BET 0x03800000 /* bus error type */
1356 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */
1357 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */
1358 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */
1359 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */
1360 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */
1361 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */
1362 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */
1363 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */
1364
1365
1366 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */
1367 #define CSR_ADM_AIE 0x84
1368 /* See CSR16 for valid bits */
1369
1370
1371 /* CSR18 - Command Register */
1372 #define CSR_ADM_CR 0x88
1373 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */
1374 #define ADM_CR_SINT 0x00000002 /* software interrupt */
1375 #define ADM_CR_DRT 0x0000000c /* drain receive threshold */
1376 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */
1377 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */
1378 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */
1379 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */
1380 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */
1381 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern
1382 data register pointer */
1383 /* 16 - 31 are automatically recalled from the EEPROM */
1384 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */
1385 #define ADM_CR_PM 0x00080000 /* power management enable */
1386 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */
1387 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */
1388 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */
1389 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */
1390 #define ADM_CR_AUXCL 0x30000000 /* aux current load */
1391 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */
1392
1393
1394 /* CSR19 - PCI bus performance counter */
1395 #define CSR_ADM_PCIC 0x8c
1396 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of
1397 last bus-master
1398 transaction */
1399 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks
1400 between read request
1401 and access completed */
1402
1403 /* CSR20 - Power Management Control/Status Register */
1404 #define CSR_ADM_PMCSR 0x90
1405 /*
1406 * This register is also mapped into the PCI configuration
1407 * space as the PMCSR.
1408 */
1409
1410
1411 /* CSR23 - Transmit Burst Count/Time Out Register */
1412 #define CSR_ADM_TXBR 0x9c
1413 #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */
1414 #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */
1415
1416
1417 /* CSR24 - Flash ROM Port Register */
1418 #define CSR_ADM_FROM 0xa0
1419 #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */
1420 #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */
1421 #define ADM_FROM_ADDR_SHIFT 8
1422 #define ADM_FROM_WEN 0x04000000 /* write enable */
1423 #define ADM_FROM_REN 0x08000000 /* read enable */
1424 #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else
1425 pin 87 is fd/col LED pin */
1426
1427
1428 /* CSR25 - Physical Address Register 0 */
1429 #define CSR_ADM_PAR0 0xa4
1430
1431
1432 /* CSR26 - Physical Address Register 1 */
1433 #define CSR_ADM_PAR1 0xa8
1434
1435
1436 /* CSR27 - Multicast Address Register 0 */
1437 #define CSR_ADM_MAR0 0xac
1438
1439
1440 /* CSR28 - Multicast Address Register 1 */
1441 #define CSR_ADM_MAR1 0xb0
1442
1443
1444 /* Internal PHY registers are mapped here (lower 16 bits valid) */
1445
1446 #define CSR_ADM_BMCR 0xb4
1447 #define CSR_ADM_BMSR 0xb8
1448 #define CSR_ADM_PHYIDR1 0xbc
1449 #define CSR_ADM_PHYIDR2 0xc0
1450 #define CSR_ADM_ANAR 0xc4
1451 #define CSR_ADM_ANLPAR 0xc8
1452 #define CSR_ADM_ANER 0xcc
1453
1454 /* XCVR Mode Control Register */
1455 #define CSR_ADM_XMC 0xd0
1456 #define ADM_XMC_LD 0x00000800 /* long distance mode
1457 (low squelch enable) */
1458
1459
1460 /* XCVR Configuration Information and Interrupt Status Register */
1461 #define CSR_ADM_XCIIS 0xd4
1462 #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */
1463 #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */
1464 #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */
1465 #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */
1466 #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */
1467 #define ADM_XCIIS_RFD 0x0020 /* remote fault */
1468 #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */
1469 #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */
1470 #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */
1471 #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */
1472
1473
1474 /* XCVR Interrupt Enable Register */
1475 #define CSR_ADM_XIE 0xd8
1476 /* Bits are as for XCIIS */
1477
1478
1479 /* XCVR 100baseTX PHY Control/Status Register */
1480 #define CSR_ADM_100CTR 0xdc
1481 #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */
1482 #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */
1483 #define ADM_100CTR_CMODE 0x001c /* current operating mode */
1484 #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */
1485 #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */
1486 #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */
1487 /* 0x000c reserved */
1488 /* 0x0010 reserved */
1489 #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */
1490 #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */
1491 #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */
1492 #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */
1493 #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */
1494 #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */
1495 #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */
1496 #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage:
1497 0 == 1.0 VPP
1498 1 == 1.4 VPP */
1499 #define ADM_100CTR_ANC 0x1000 /* autoneg completed */
1500 #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */
1501
1502 /* Operation Mode Register (AN983) */
1503 #define CSR_ADM983_OPMODE 0xfc
1504 #define ADM983_OPMODE_SPEED 0x80000000 /* 1 == 100, 0 == 10 */
1505 #define ADM983_OPMODE_FD 0x40000000 /* 1 == fd, 0 == hd */
1506 #define ADM983_OPMODE_LINK 0x20000000 /* 1 == link, 0 == no link */
1507 #define ADM983_OPMODE_EERLOD 0x04000000 /* reload from EEPROM */
1508 #define ADM983_OPMODE_SingleChip 0x00000007 /* single-chip mode */
1509 #define ADM983_OPMODE_MacOnly 0x00000004 /* MAC-only mode */
1510
1511 /*
1512 * Xircom X3201-3 registers
1513 */
1514
1515 /* Power Management Register */
1516 #define CSR_X3201_PMR TULIP_CSR16
1517 #define X3201_PMR_EDINT 0x0000000f /* energy detect interval */
1518 #define X3201_PMR_EDEN 0x00000100 /* energy detect enable */
1519 #define X3201_PMR_MPEN 0x00000200 /* magic packet enable */
1520 #define X3201_PMR_WOLEN 0x00000400 /* Wake On Lan enable */
1521 #define X3201_PMR_PMGP0EN 0x00001000 /* GP0 change enable */
1522 #define X3201_PMR_PMLCEN 0x00002000 /* link change enable */
1523 #define X3201_PMR_WOLTMEN 0x00008000 /* WOL template mem enable */
1524 #define X3201_PMR_EP 0x00010000 /* energy present */
1525 #define X3201_PMR_LP 0x00200000 /* link present */
1526 #define X3201_PMR_EDES 0x01000000 /* ED event status */
1527 #define X3201_PMR_MPES 0x02000000 /* MP event status */
1528 #define X3201_PMR_WOLES 0x04000000 /* WOL event status */
1529 #define X3201_PMR_WOLPS 0x08000000 /* WOL process status */
1530 #define X3201_PMR_GP0ES 0x10000000 /* GP0 event status */
1531 #define X3201_PMR_LCES 0x20000000 /* LC event status */
1532
1533 /*
1534 * Davicom DM9102 registers.
1535 */
1536
1537 /* PHY Status Register */
1538 #define CSR_DM_PHYSTAT TULIP_CSR12
1539 #define DM_PHYSTAT_10 0x00000001 /* 10Mb/s */
1540 #define DM_PHYSTAT_100 0x00000002 /* 100Mb/s */
1541 #define DM_PHYSTAT_FDX 0x00000004 /* full-duplex */
1542 #define DM_PHYSTAT_LINK 0x00000008 /* link up */
1543 #define DM_PHYSTAT_RXLOCK 0x00000010 /* RX-lock */
1544 #define DM_PHYSTAT_SIGNAL 0x00000020 /* signal detection */
1545 #define DM_PHYSTAT_UTPSIG 0x00000040 /* UTP SIG */
1546 #define DM_PHYSTAT_GPED 0x00000080 /* general PHY reset control */
1547 #define DM_PHYSTAT_GEPC 0x00000100 /* GPED bits control */
1548
1549
1550 /* Sample Frame Access Register */
1551 #define CSR_DM_SFAR TULIP_CSR13
1552
1553
1554 /* Sample Frame Data Register */
1555 #define CSR_DM_SFDR TULIP_CSR14
1556 /* See 21143 SIAGEN register */
1557
1558 /*
1559 * ASIX AX88140A and AX88141 registers.
1560 */
1561
1562 /* CSR13 - Filtering Index */
1563 #define CSR_AX_FILTIDX TULIP_CSR13
1564
1565 /* CSR14 - Filtering data */
1566 #define CSR_AX_FILTDATA TULIP_CSR14
1567
1568 /* Filtering Index values */
1569 #define AX_FILTIDX_PAR0 0x00000000
1570 #define AX_FILTIDX_PAR1 0x00000001
1571 #define AX_FILTIDX_MAR0 0x00000002
1572 #define AX_FILTIDX_MAR1 0x00000003
1573
1574 #endif /* _DEV_IC_TULIPREG_H_ */
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