/[gxemul]/trunk/src/include/tc_ioasicreg.h
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Contents of /trunk/src/include/tc_ioasicreg.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9216 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============
1 /* gxemul: $Id: tc_ioasicreg.h,v 1.3 2005/03/05 12:34:03 debug Exp $ */
2
3 #ifndef TC_IOASICREG_H
4 #define TC_IOASICREG_H
5
6 /* $NetBSD: ioasicreg.h,v 1.6 2000/07/17 02:18:17 thorpej Exp $ */
7
8 /*
9 * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
10 * All Rights Reserved.
11 *
12 * Permission to use, copy, modify and distribute this software and
13 * its documentation is hereby granted, provided that both the copyright
14 * notice and this permission notice appear in all copies of the
15 * software, derivative works or modified versions, and any portions
16 * thereof, and that both notices appear in supporting documentation.
17 *
18 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
19 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
20 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
21 *
22 * Carnegie Mellon requests users of this software to return to
23 *
24 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
25 * School of Computer Science
26 * Carnegie Mellon University
27 * Pittsburgh PA 15213-3890
28 *
29 * any improvements or extensions that they make and grant Carnegie the
30 * rights to redistribute these changes.
31 */
32
33 /*-
34 * Copyright (c) 1992, 1993
35 * The Regents of the University of California. All rights reserved.
36 *
37 * This code is derived from software contributed to Berkeley by
38 * The Mach Operating System project at Carnegie-Mellon University,
39 * Ralph Campbell and Rick Macklem.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by the University of
52 * California, Berkeley and its contributors.
53 * 4. Neither the name of the University nor the names of its contributors
54 * may be used to endorse or promote products derived from this software
55 * without specific prior written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 * SUCH DAMAGE.
68 *
69 * @(#)asic.h 8.1 (Berkeley) 6/10/93
70 */
71
72 /*
73 * Slot definitions
74 */
75
76 #define IOASIC_SLOT_0_START 0x000000
77 #define IOASIC_SLOT_1_START 0x040000
78 #define IOASIC_SLOT_2_START 0x080000
79 #define IOASIC_SLOT_3_START 0x0c0000
80 #define IOASIC_SLOT_4_START 0x100000
81 #define IOASIC_SLOT_5_START 0x140000
82 #define IOASIC_SLOT_6_START 0x180000
83 #define IOASIC_SLOT_7_START 0x1c0000
84 #define IOASIC_SLOT_8_START 0x200000
85 #define IOASIC_SLOT_9_START 0x240000
86 #define IOASIC_SLOT_10_START 0x280000
87 #define IOASIC_SLOT_11_START 0x2c0000
88 #define IOASIC_SLOT_12_START 0x300000
89 #define IOASIC_SLOT_13_START 0x340000
90 #define IOASIC_SLOT_14_START 0x380000
91 #define IOASIC_SLOT_15_START 0x3c0000
92 #define IOASIC_SLOTS_END 0x3fffff
93
94 /*
95 * Register offsets (slot 1)
96 */
97
98 #define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
99 #define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
100 #define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
101 #define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
102 #define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
103 #define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
104 #define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
105 #define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
106 #define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
107 #define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
108 #define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
109 #define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
110 #define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
111 #define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
112 #define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
113 #define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
114 #define IOASIC_CSR IOASIC_SLOT_1_START+0x100
115 #define IOASIC_INTR IOASIC_SLOT_1_START+0x110
116 #define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
117 #define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
118 #define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
119 #define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
120 #define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
121 #define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
122 #define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
123 #define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
124 #define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
125 #define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
126 #define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
127 #define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
128 #define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/
129
130 /* System Status and control Register (SSR). */
131 #define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */
132 #define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */
133 #define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */
134 #define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */
135 #define IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */
136 #define IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */
137 #define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */
138 #define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */
139 #define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */
140 #define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
141 #define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
142 #define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */
143 #define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */
144 #define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */
145 /* low 16 bits are rw gp outputs */
146 #define IOASIC_CSR_DIAGDN 0x00008000 /* rw */
147 #define IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */
148 #define IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */
149 #define IOASIC_CSR_ISDN_ENABLE 0x00001000 /* rw - 3000/maxine */
150 #define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */
151 #define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */
152 #define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */
153 #define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */
154
155 /* System Interrupt Register (and Interrupt Mask Register). */
156 #define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
157 #define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */
158 #define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
159 #define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
160 #define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
161 #define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */
162 #define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
163 #define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
164 #define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */
165 #define IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz - 3000/maxine */
166 #define IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz - 3000/maxine */
167 #define IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz - 3000/maxine */
168 #define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */
169 #define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */
170 #define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */
171 #define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */
172
173 /* low 16 bits are model-dependent; see also model specific *.h */
174 #define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */
175 #define IOASIC_INTR_ISDN 0x00002000 /* ro - 3000 */
176 #define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */
177 #define IOASIC_INTR_SEC_CON 0x00000200 /* ro */
178 #define IOASIC_INTR_SCSI 0x00000200 /* ro - DS */
179 #define IOASIC_INTR_LANCE 0x00000100 /* ro */
180 #define IOASIC_INTR_SCC_1 0x00000080 /* ro */
181 #define IOASIC_INTR_SCC_0 0x00000040 /* ro */
182 #define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */
183 #define IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */
184 #define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */
185
186 /* DMA pointer registers (SCSI, Comm, ...) */
187
188 #define IOASIC_DMA_ADDR(p) \
189 ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f))
190 #define IOASIC_DMA_BLOCKSIZE 0x1000
191
192 /* For the LANCE DMA pointer register initialization the above suffices */
193
194 /* More SCSI DMA registers */
195
196 #define IOASIC_SCR_STATUS 0x00000004
197 #define IOASIC_SCR_WORD 0x00000003
198
199 /* Various Decode registers */
200
201 #define IOASIC_DECODE_HW_ADDRESS 0x000003f0
202 #define IOASIC_DECODE_CHIP_SELECT 0x0000000f
203
204 /*
205 * And slot assignments.
206 */
207 #define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
208 #define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)
209
210
211 #endif /* TC_IOASICREG_H */
212
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