/[gxemul]/trunk/src/include/siireg.h
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Contents of /trunk/src/include/siireg.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 8670 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /* gxemul: $Id: siireg.h,v 1.3 2005/03/05 12:34:03 debug Exp $ */
2 /* $NetBSD: siireg.h,v 1.4 1994/10/26 21:09:22 cgd Exp $ */
3
4 /*
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * Ralph Campbell.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * @(#)siireg.h 8.1 (Berkeley) 6/10/93
40 *
41 * sii.h --
42 *
43 * SII registers.
44 *
45 * Copyright (C) 1989 Digital Equipment Corporation.
46 * Permission to use, copy, modify, and distribute this software and
47 * its documentation for any purpose and without fee is hereby granted,
48 * provided that the above copyright notice appears in all copies.
49 * Digital Equipment Corporation makes no representations about the
50 * suitability of this software for any purpose. It is provided "as is"
51 * without express or implied warranty.
52 *
53 * from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/sii.h,
54 * v 1.2 89/08/15 19:53:04 rab Exp SPRITE (DECWRL)
55 */
56
57 #ifndef _SII
58 #define _SII
59
60 /*
61 * SII hardware registers
62 */
63 typedef volatile struct {
64 u_short sdb; /* SCSI Data Bus and Parity */
65 u_short pad0;
66 u_short sc1; /* SCSI Control Signals One */
67 u_short pad1;
68 u_short sc2; /* SCSI Control Signals Two */
69 u_short pad2;
70 u_short csr; /* Control/Status register */
71 u_short pad3;
72 u_short id; /* Bus ID register */
73 u_short pad4;
74 u_short slcsr; /* Select Control and Status Register */
75 u_short pad5;
76 u_short destat; /* Selection Detector Status Register */
77 u_short pad6;
78 u_short dstmo; /* DSSI Timeout Register */
79 u_short pad7;
80 u_short data; /* Data Register */
81 u_short pad8;
82 u_short dmctrl; /* DMA Control Register */
83 u_short pad9;
84 u_short dmlotc; /* DMA Length of Transfer Counter */
85 u_short pad10;
86 u_short dmaddrl; /* DMA Address Register Low */
87 u_short pad11;
88 u_short dmaddrh; /* DMA Address Register High */
89 u_short pad12;
90 u_short dmabyte; /* DMA Initial Byte Register */
91 u_short pad13;
92 u_short stlp; /* DSSI Short Target List Pointer */
93 u_short pad14;
94 u_short ltlp; /* DSSI Long Target List Pointer */
95 u_short pad15;
96 u_short ilp; /* DSSI Initiator List Pointer */
97 u_short pad16;
98 u_short dsctrl; /* DSSI Control Register */
99 u_short pad17;
100 u_short cstat; /* Connection Status Register */
101 u_short pad18;
102 u_short dstat; /* Data Transfer Status Register */
103 u_short pad19;
104 u_short comm; /* Command Register */
105 u_short pad20;
106 u_short dictrl; /* Diagnostic Control Register */
107 u_short pad21;
108 u_short clock; /* Diagnostic Clock Register */
109 u_short pad22;
110 u_short bhdiag; /* Bus Handler Diagnostic Register */
111 u_short pad23;
112 u_short sidiag; /* SCSI IO Diagnostic Register */
113 u_short pad24;
114 u_short dmdiag; /* Data Mover Diagnostic Register */
115 u_short pad25;
116 u_short mcdiag; /* Main Control Diagnostic Register */
117 u_short pad26;
118 } SIIRegs;
119
120 /*
121 * SC1 - SCSI Control Signals One
122 */
123 #define SII_SC1_MSK 0x1ff /* All possible signals on the bus */
124 #define SII_SC1_SEL 0x80 /* SCSI SEL signal active on bus */
125 #define SII_SC1_ATN 0x08 /* SCSI ATN signal active on bus */
126
127 /*
128 * SC2 - SCSI Control Signals Two
129 */
130 #define SII_SC2_IGS 0x8 /* SCSI drivers for initiator mode */
131
132 /*
133 * CSR - Control/Status Register
134 */
135 #define SII_HPM 0x10 /* SII in on an arbitrated SCSI bus */
136 #define SII_RSE 0x08 /* 1 = respond to reselections */
137 #define SII_SLE 0x04 /* 1 = respond to selections */
138 #define SII_PCE 0x02 /* 1 = report parity errors */
139 #define SII_IE 0x01 /* 1 = enable interrupts */
140
141 /*
142 * ID - Bus ID Register
143 */
144 #define SII_ID_IO 0x8000 /* I/O */
145
146 /*
147 * DESTAT - Selection Detector Status Register
148 */
149 #define SII_IDMSK 0x7 /* ID of target reselected the SII */
150
151 /*
152 * DMCTRL - DMA Control Register
153 */
154 #define SII_ASYNC 0x00 /* REQ/ACK Offset for async mode */
155 #define SII_SYNC 0x03 /* REQ/ACK Offset for sync mode */
156
157 /*
158 * DMLOTC - DMA Length Of Transfer Counter
159 */
160 #define SII_TCMSK 0x1fff /* transfer count mask */
161
162 /*
163 * CSTAT - Connection Status Register
164 */
165 #define SII_CI 0x8000 /* composite interrupt bit for CSTAT */
166 #define SII_DI 0x4000 /* composite interrupt bit for DSTAT */
167 #define SII_RST 0x2000 /* 1 if reset is asserted on SCSI bus */
168 #define SII_BER 0x1000 /* Bus error */
169 #define SII_OBC 0x0800 /* Out_en Bit Cleared (DSSI mode) */
170 #define SII_TZ 0x0400 /* Target pointer Zero (STLP or LTLP is zero) */
171 #define SII_BUF 0x0200 /* Buffer service - outbound pkt to non-DSSI */
172 #define SII_LDN 0x0100 /* List element Done */
173 #define SII_SCH 0x0080 /* State Change */
174 #define SII_CON 0x0040 /* SII is Connected to another device */
175 #define SII_DST 0x0020 /* SII was Destination of current transfer */
176 #define SII_TGT 0x0010 /* SII is operating as a Target */
177 #define SII_STATE_MSK 0x0070 /* State Mask */
178 #define SII_SWA 0x0008 /* Selected With Attention */
179 #define SII_SIP 0x0004 /* Selection In Progress */
180 #define SII_LST 0x0002 /* Lost arbitration */
181
182 /*
183 * DSTAT - Data Transfer Status Register
184 */
185 #define SII_DNE 0x2000 /* DMA transfer Done */
186 #define SII_TCZ 0x1000 /* Transfer Count register is Zero */
187 #define SII_TBE 0x0800 /* Transmit Buffer Empty */
188 #define SII_IBF 0x0400 /* Input Buffer Full */
189 #define SII_IPE 0x0200 /* Incoming Parity Error */
190 #define SII_OBB 0x0100 /* Odd Byte Boundry */
191 #define SII_MIS 0x0010 /* Phase Mismatch */
192 #define SII_ATN 0x0008 /* ATN set by initiator if in Target mode */
193 #define SII_MSG 0x0004 /* current bus state of MSG */
194 #define SII_CD 0x0002 /* current bus state of C/D */
195 #define SII_IO 0x0001 /* current bus state of I/O */
196 #define SII_PHASE_MSK 0x0007 /* Phase Mask */
197
198 /*
199 * The different phases.
200 */
201 #define SII_MSG_IN_PHASE 0x7
202 #define SII_MSG_OUT_PHASE 0x6
203 #define SII_STATUS_PHASE 0x3
204 #define SII_CMD_PHASE 0x2
205 #define SII_DATA_IN_PHASE 0x1
206 #define SII_DATA_OUT_PHASE 0x0
207
208 /*
209 * COMM - Command Register
210 */
211 #define SII_DMA 0x8000 /* DMA mode */
212 #define SII_DO_RST 0x4000 /* Assert reset on SCSI bus for 25 usecs */
213 #define SII_RSL 0x1000 /* 0 = select, 1 = reselect desired device */
214
215 /* Commands: I - Initiator, T - Target, D - Disconnected */
216 #define SII_INXFER 0x0800 /* Information Transfer command (I,T) */
217 #define SII_SELECT 0x0400 /* Select command (D) */
218 #define SII_REQDATA 0x0200 /* Request Data command (T) */
219 #define SII_DISCON 0x0100 /* Disconnect command (I,T,D) */
220 #define SII_CHRESET 0x0080 /* Chip Reset command (I,T,D) */
221
222 /* Command state bits same as connection status register */
223 /* Command phase bits same as data transfer status register */
224
225 /*
226 * DICTRL - Diagnostic Control Register
227 */
228 #define SII_PRE 0x4 /* Enable the SII to drive the SCSI bus */
229
230 #define SII_WAIT_COUNT 10000 /* Delay count used for the SII chip */
231 /*
232 * Max DMA transfer length for SII
233 * The SII chip only has a 13 bit counter. If 8192 is used as the max count,
234 * you can't tell the difference between a count of zero and 8192.
235 * 8190 is used instead of 8191 so the count is even.
236 */
237 #define SII_MAX_DMA_XFER_LENGTH 8192
238
239 #endif /* _SII */

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