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++ trunk/HISTORY (local) $Id: HISTORY,v 1.1539 2007/05/01 04:03:51 debug Exp $ 20070415 Landisk PCLOCK should be 33.33 MHz, not 50 MHz. (This makes the clock run at correct speed.) FINALLY found and fixed the bug which caused OpenBSD/landisk to randomly bug out: an &-sign was missing in the special case handling of FPSCR in the 'LDS.L @Rm+,FPSCR' instruction. Adding similar special case handling for 'LDC.L @Rm+,SR' (calling sh_update_sr() instead of just loading). Implementing the 'FCNVSD FPUL,DRn' and 'FCNVDS DRm,FPUL' SuperH instructions. The 'LDC Rm,SR' instruction now immediately breaks out of the dyntrans loop if an interrupt is to be triggered. 20070416 In memory_rw.c, if mapping a page as writable, make sure to invalidate code translations even if the data access was a read. Minor SuperH updates. 20070418 Removing the dummy M68K emulation mode. Minor SH update (turning unnecessary sts_mach_rn, sts_macl_rn, and sts_pr_rn instruction handlers into mov_rm_rn). 20070419 Beginning to add a skeleton for an M88K mode: Adding a hack to allow OpenBSD/m88k a.out binaries to be loaded, and disassembly of a few simple 88K instructions. Commenting out the 'LDC Rm,SR' fix from a few days ago, because it made Linux/dreamcast bug out. Adding a hack to dev_sh4.c (an extra translation cache invalidation), which allows OpenBSD/landisk to boot ok after an install. Upgrading the Landisk machine mode to stable, updating documentation, etc. 20070420 Experimenting with adding a PCI controller (pcic) to dev_sh4. Adding a dummy Realtek 8139C+ skeleton device (dev_rtl8139c). Implementing the first M88K instructions (br, or[.u] imm), and adding disassembly of some more instructions. 20070421 Continuing a little on dev_rtl8139c. 20070422 Implementing the 9346 EEPROM "read" command for dev_rtl8139c. Finally found and fixed an old bug in the log n symbol search (it sometimes missed symbols). Debug trace (-i, -t etc) should now show more symbols. :-) 20070423 Continuing a little on M88K disassembly. 20070428 Fixing a memset arg order bug in src/net/net.c (thanks to Nigel Horne for noticing the bug). Applying parts of a patch from Carl van Schaik to clear out bottom bits of MIPS addresses more correctly, when using large page sizes, and doing some other minor cleanup/refactoring. Fixing a couple of warnings given by gcc with the -W option (a few more warnings than just plain -Wall). Reducing SuperH dyntrans physical address space from 64-bit to 32-bit (since SH5/SH64 isn't imlemented yet anyway). Adding address-to-symbol annotation to a few more instructions in the SuperH instruction trace output. Beginning regression testing for the next release. Reverting the value of SCIF_DELAYED_TX_VALUE from 1 to 2, because OpenBSD/landisk may otherwise hang randomly. 20070429 The ugly hack/workaround to get OpenBSD/landisk booting without crashing does NOT work anymore (with the April 21 snapshot of OpenBSD/landisk). Strangely enough, removing the hack completely causes OpenBSD/landisk to work (!). More regression testing (re-testing everything SuperH-related, and some other things). Cobalt interrupts were actually broken; fixing by commenting out the DEC21143s in the Cobalt machine. 20070430 More regression testing. 20070501 Updating the OpenBSD/landisk install instructions to use 4.1 instead of the current snapshot. GAAAH! OpenBSD/landisk 4.1 _needs_ the ugly hack/workaround; reintroducing it again. (The 4.1 kernel is actually from 2007-03-11.) Simplifying the NetBSD/evbarm install instructions a bit. More regression testing. ============== RELEASE 0.4.5.1 ==============
1 | /* GXemul: $Id: sh4_scireg.h,v 1.3 2007/04/16 15:11:01 debug Exp $ */ |
2 | /* $OpenBSD: scireg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */ |
3 | /* $NetBSD: scireg.h,v 1.8 2003/07/01 11:49:37 uwe Exp $ */ |
4 | |
5 | #ifndef SH4_SCIREG_H |
6 | #define SH4_SCIREG_H |
7 | |
8 | /* GXemul base address for SCI-connected devices: */ |
9 | #define SCI_DEVICE_BASE 0x110000000ULL |
10 | |
11 | |
12 | /*- |
13 | * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. |
14 | * |
15 | * Redistribution and use in source and binary forms, with or without |
16 | * modification, are permitted provided that the following conditions |
17 | * are met: |
18 | * 1. Redistributions of source code must retain the above copyright |
19 | * notice, this list of conditions and the following disclaimer. |
20 | * 2. Redistributions in binary form must reproduce the above copyright |
21 | * notice, this list of conditions and the following disclaimer in the |
22 | * documentation and/or other materials provided with the distribution. |
23 | * 3. The name of the author may not be used to endorse or promote products |
24 | * derived from this software without specific prior written permission. |
25 | * |
26 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
27 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
28 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
29 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
30 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
31 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
32 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
33 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
36 | */ |
37 | |
38 | /* |
39 | * Serial Communication Interface (SCI) |
40 | */ |
41 | |
42 | #if 0 |
43 | !defined(SH4) |
44 | |
45 | /* SH3 definitions */ |
46 | |
47 | #define SHREG_SCSMR (*(volatile unsigned char *) 0xFFFFFE80) |
48 | #define SHREG_SCBRR (*(volatile unsigned char *) 0xFFFFFE82) |
49 | #define SHREG_SCSCR (*(volatile unsigned char *) 0xFFFFFE84) |
50 | #define SHREG_SCTDR (*(volatile unsigned char *) 0xFFFFFE86) |
51 | #define SHREG_SCSSR (*(volatile unsigned char *) 0xFFFFFE88) |
52 | #define SHREG_SCRDR (*(volatile unsigned char *) 0xFFFFFE8A) |
53 | #define SHREG_SCSPDR (*(volatile unsigned char *) 0xf4000136) |
54 | |
55 | #else |
56 | |
57 | /* SH4 definitions */ |
58 | |
59 | #define SHREG_SCSMR /* (*(volatile unsigned char *) */ 0xffe00000 |
60 | #define SHREG_SCBRR /* (*(volatile unsigned char *) */ 0xffe00004 |
61 | #define SHREG_SCSCR /* (*(volatile unsigned char *) */ 0xffe00008 |
62 | #define SHREG_SCTDR /* (*(volatile unsigned char *) */ 0xffe0000c |
63 | #define SHREG_SCSSR /* (*(volatile unsigned char *) */ 0xffe00010 |
64 | #define SHREG_SCRDR /* (*(volatile unsigned char *) */ 0xffe00014 |
65 | #define SHREG_SCSPTR /* (*(volatile unsigned char *) */ 0xffe0001c |
66 | |
67 | #endif |
68 | |
69 | #define SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ |
70 | #define SCSCR_RIE 0x40 /* Receive Interrupt Enable */ |
71 | #define SCSCR_TE 0x20 /* Transmit Enable */ |
72 | #define SCSCR_RE 0x10 /* Receive Enable */ |
73 | #define SCSCR_MPIE 0x08 /* Multi Processor Interrupt Enable */ |
74 | #define SCSCR_TEIE 0x04 /* Transmit End Interrupt Enable */ |
75 | #define SCSCR_CKE1 0x02 /* ClocK Enable 1 */ |
76 | #define SCSCR_CKE0 0x01 /* ClocK Enable 0 */ |
77 | |
78 | #define SCSSR_TDRE 0x80 |
79 | #define SCSSR_RDRF 0x40 |
80 | #define SCSSR_ORER 0x20 |
81 | #define SCSSR_FER 0x10 |
82 | #define SCSSR_PER 0x08 |
83 | |
84 | #define SCSPTR_SPB1IO 0x08 |
85 | #define SCSPTR_SPB1DT 0x04 |
86 | #define SCSPTR_SPB0IO 0x02 |
87 | #define SCSPTR_SPB0DT 0x01 |
88 | |
89 | #if defined(SH3) |
90 | #define SCSPDR_SCP0DT 0x01 |
91 | #endif |
92 | |
93 | |
94 | #endif /* SH4_SCIREG_H */ |
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