/[gxemul]/trunk/src/include/sh4_pcicreg.h
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Contents of /trunk/src/include/sh4_pcicreg.h

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Revision 40 - (show annotations)
Mon Oct 8 16:22:11 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6120 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1539 2007/05/01 04:03:51 debug Exp $
20070415	Landisk PCLOCK should be 33.33 MHz, not 50 MHz. (This makes
		the clock run at correct speed.)
		FINALLY found and fixed the bug which caused OpenBSD/landisk
		to randomly bug out: an &-sign was missing in the special case
		handling of FPSCR in the 'LDS.L @Rm+,FPSCR' instruction.
		Adding similar special case handling for 'LDC.L @Rm+,SR'
		(calling sh_update_sr() instead of just loading).
		Implementing the 'FCNVSD FPUL,DRn' and 'FCNVDS DRm,FPUL'
		SuperH instructions.
		The 'LDC Rm,SR' instruction now immediately breaks out of the
		dyntrans loop if an interrupt is to be triggered.
20070416	In memory_rw.c, if mapping a page as writable, make sure to
		invalidate code translations even if the data access was a
		read.
		Minor SuperH updates.
20070418	Removing the dummy M68K emulation mode.
		Minor SH update (turning unnecessary sts_mach_rn, sts_macl_rn,
		and sts_pr_rn instruction handlers into mov_rm_rn).
20070419	Beginning to add a skeleton for an M88K mode: Adding a hack to
		allow OpenBSD/m88k a.out binaries to be loaded, and disassembly
		of a few simple 88K instructions.
		Commenting out the 'LDC Rm,SR' fix from a few days ago, because
		it made Linux/dreamcast bug out.
		Adding a hack to dev_sh4.c (an extra translation cache
		invalidation), which allows OpenBSD/landisk to boot ok after
		an install. Upgrading the Landisk machine mode to stable,
		updating documentation, etc.
20070420	Experimenting with adding a PCI controller (pcic) to dev_sh4.
		Adding a dummy Realtek 8139C+ skeleton device (dev_rtl8139c).
		Implementing the first M88K instructions (br, or[.u] imm), and
		adding disassembly of some more instructions.
20070421	Continuing a little on dev_rtl8139c.
20070422	Implementing the 9346 EEPROM "read" command for dev_rtl8139c.
		Finally found and fixed an old bug in the log n symbol search
		(it sometimes missed symbols). Debug trace (-i, -t etc) should
		now show more symbols. :-)
20070423	Continuing a little on M88K disassembly.
20070428	Fixing a memset arg order bug in src/net/net.c (thanks to
		Nigel Horne for noticing the bug).
		Applying parts of a patch from Carl van Schaik to clear out
		bottom bits of MIPS addresses more correctly, when using large
		page sizes, and doing some other minor cleanup/refactoring.
		Fixing a couple of warnings given by gcc with the -W option (a
		few more warnings than just plain -Wall).
		Reducing SuperH dyntrans physical address space from 64-bit to
		32-bit (since SH5/SH64 isn't imlemented yet anyway).
		Adding address-to-symbol annotation to a few more instructions
		in the SuperH instruction trace output.
		Beginning regression testing for the next release.
		Reverting the value of SCIF_DELAYED_TX_VALUE from 1 to 2,
		because OpenBSD/landisk may otherwise hang randomly.
20070429	The ugly hack/workaround to get OpenBSD/landisk booting without
		crashing does NOT work anymore (with the April 21 snapshot
		of OpenBSD/landisk). Strangely enough, removing the hack
		completely causes OpenBSD/landisk to work (!).
		More regression testing (re-testing everything SuperH-related,
		and some other things).
		Cobalt interrupts were actually broken; fixing by commenting
		out the DEC21143s in the Cobalt machine.
20070430	More regression testing.
20070501	Updating the OpenBSD/landisk install instructions to use
		4.1 instead of the current snapshot.
		GAAAH! OpenBSD/landisk 4.1 _needs_ the ugly hack/workaround;
		reintroducing it again. (The 4.1 kernel is actually from
		2007-03-11.)
		Simplifying the NetBSD/evbarm install instructions a bit.
		More regression testing.

==============  RELEASE 0.4.5.1  ==============
1 /* GXemul: $Id: sh4_pcicreg.h,v 1.1 2007/04/20 06:22:28 debug Exp $ */
2 /* $OpenBSD: pcicreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */
3 /* $NetBSD: pcicreg.h,v 1.2 2005/12/11 12:18:58 christos Exp $ */
4
5 #ifndef SH4_PCICREG_H
6 #define SH4_PCICREG_H
7
8 /*-
9 * Copyright (c) 2005 NONAKA Kimihiro
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /* #include <sh/devreg.h> */
35
36 /*
37 * PCI Controller
38 */
39
40 #define SH4_PCIC 0xfe200000
41
42 #define SH4_PCIC_IO 0xfe240000
43 #define SH4_PCIC_IO_SIZE 0x00040000
44 #define SH4_PCIC_IO_MASK (SH4_PCIC_IO_SIZE-1)
45 #define SH4_PCIC_MEM 0xfd000000
46 #define SH4_PCIC_MEM_SIZE 0x01000000
47 #define SH4_PCIC_MEM_MASK (SH4_PCIC_MEM_SIZE-1)
48
49 #define SH4_PCICONF (SH4_PCIC+0x000) /* 32bit */
50 #define SH4_PCICONF0 (SH4_PCICONF+0x00) /* 32bit */
51 #define SH4_PCICONF1 (SH4_PCICONF+0x04) /* 32bit */
52 #define SH4_PCICONF2 (SH4_PCICONF+0x08) /* 32bit */
53 #define SH4_PCICONF3 (SH4_PCICONF+0x0c) /* 32bit */
54 #define SH4_PCICONF4 (SH4_PCICONF+0x10) /* 32bit */
55 #define SH4_PCICONF5 (SH4_PCICONF+0x14) /* 32bit */
56 #define SH4_PCICONF6 (SH4_PCICONF+0x18) /* 32bit */
57 #define SH4_PCICONF7 (SH4_PCICONF+0x1c) /* 32bit */
58 #define SH4_PCICONF8 (SH4_PCICONF+0x20) /* 32bit */
59 #define SH4_PCICONF9 (SH4_PCICONF+0x24) /* 32bit */
60 #define SH4_PCICONF10 (SH4_PCICONF+0x28) /* 32bit */
61 #define SH4_PCICONF11 (SH4_PCICONF+0x2c) /* 32bit */
62 #define SH4_PCICONF12 (SH4_PCICONF+0x30) /* 32bit */
63 #define SH4_PCICONF13 (SH4_PCICONF+0x34) /* 32bit */
64 #define SH4_PCICONF14 (SH4_PCICONF+0x38) /* 32bit */
65 #define SH4_PCICONF15 (SH4_PCICONF+0x3c) /* 32bit */
66 #define SH4_PCICONF16 (SH4_PCICONF+0x40) /* 32bit */
67 #define SH4_PCICONF17 (SH4_PCICONF+0x44) /* 32bit */
68 #define SH4_PCICR (SH4_PCIC+0x100) /* 32bit */
69 #define SH4_PCILSR0 (SH4_PCIC+0x104) /* 32bit */
70 #define SH4_PCILSR1 (SH4_PCIC+0x108) /* 32bit */
71 #define SH4_PCILAR0 (SH4_PCIC+0x10c) /* 32bit */
72 #define SH4_PCILAR1 (SH4_PCIC+0x110) /* 32bit */
73 #define SH4_PCIINT (SH4_PCIC+0x114) /* 32bit */
74 #define SH4_PCIINTM (SH4_PCIC+0x118) /* 32bit */
75 #define SH4_PCIALR (SH4_PCIC+0x11c) /* 32bit */
76 #define SH4_PCICLR (SH4_PCIC+0x120) /* 32bit */
77 #define SH4_PCIAINT (SH4_PCIC+0x130) /* 32bit */
78 #define SH4_PCIAINTM (SH4_PCIC+0x134) /* 32bit */
79 #define SH4_PCIDMABT (SH4_PCIC+0x140) /* 32bit */
80 #define SH4_PCIDPA0 (SH4_PCIC+0x180) /* 32bit */
81 #define SH4_PCIDLA0 (SH4_PCIC+0x184) /* 32bit */
82 #define SH4_PCIDTC0 (SH4_PCIC+0x188) /* 32bit */
83 #define SH4_PCIDCR0 (SH4_PCIC+0x18c) /* 32bit */
84 #define SH4_PCIDPA1 (SH4_PCIC+0x190) /* 32bit */
85 #define SH4_PCIDLA1 (SH4_PCIC+0x194) /* 32bit */
86 #define SH4_PCIDTC1 (SH4_PCIC+0x198) /* 32bit */
87 #define SH4_PCIDCR1 (SH4_PCIC+0x19c) /* 32bit */
88 #define SH4_PCIDPA2 (SH4_PCIC+0x1a0) /* 32bit */
89 #define SH4_PCIDLA2 (SH4_PCIC+0x1a4) /* 32bit */
90 #define SH4_PCIDTC2 (SH4_PCIC+0x1a8) /* 32bit */
91 #define SH4_PCIDCR2 (SH4_PCIC+0x1ac) /* 32bit */
92 #define SH4_PCIDPA3 (SH4_PCIC+0x1b0) /* 32bit */
93 #define SH4_PCIDLA3 (SH4_PCIC+0x1b4) /* 32bit */
94 #define SH4_PCIDTC3 (SH4_PCIC+0x1b8) /* 32bit */
95 #define SH4_PCIDCR3 (SH4_PCIC+0x1bc) /* 32bit */
96 #define SH4_PCIPAR (SH4_PCIC+0x1c0) /* 32bit */
97 #define SH4_PCIMBR (SH4_PCIC+0x1c4) /* 32bit */
98 #define SH4_PCIIOBR (SH4_PCIC+0x1c8) /* 32bit */
99 #define SH4_PCIPINT (SH4_PCIC+0x1cc) /* 32bit */
100 #define SH4_PCIPINTM (SH4_PCIC+0x1d0) /* 32bit */
101 #define SH4_PCICLKR (SH4_PCIC+0x1d4) /* 32bit */
102 #define SH4_PCIBCR1 (SH4_PCIC+0x1e0) /* 32bit */
103 #define SH4_PCIBCR2 (SH4_PCIC+0x1e4) /* 32bit */
104 #define SH4_PCIWCR1 (SH4_PCIC+0x1e8) /* 32bit */
105 #define SH4_PCIWCR2 (SH4_PCIC+0x1ec) /* 32bit */
106 #define SH4_PCIWCR3 (SH4_PCIC+0x1f0) /* 32bit */
107 #define SH4_PCIMCR (SH4_PCIC+0x1f4) /* 32bit */
108 #define SH4_PCIBCR3 (SH4_PCIC+0x1f8) /* 32bit: SH7751R */
109 #define SH4_PCIPCTR (SH4_PCIC+0x200) /* 32bit */
110 #define SH4_PCIPDTR (SH4_PCIC+0x204) /* 32bit */
111 #define SH4_PCIPDR (SH4_PCIC+0x220) /* 32bit */
112
113 #define PCICR_BASE 0xa5000000
114 #define PCICR_TRDSGL 0x00000200
115 #define PCICR_BYTESWAP 0x00000100
116 #define PCICR_PCIPUP 0x00000080
117 #define PCICR_BMABT 0x00000040
118 #define PCICR_MD10 0x00000020
119 #define PCICR_MD9 0x00000010
120 #define PCICR_SERR 0x00000008
121 #define PCICR_INTA 0x00000004
122 #define PCICR_RSTCTL 0x00000002
123 #define PCICR_CFINIT 0x00000001
124
125 #define PCIINT_M_LOCKON 0x00008000
126 #define PCIINT_T_TGT_ABORT 0x00004000
127 #define PCIINT_TGT_RETRY 0x00000200
128 #define PCIINT_MST_DIS 0x00000100
129 #define PCIINT_ADRPERR 0x00000080
130 #define PCIINT_SERR_DET 0x00000040
131 #define PCIINT_T_DPERR_WT 0x00000020
132 #define PCIINT_T_PERR_DET 0x00000010
133 #define PCIINT_M_TGT_ABORT 0x00000008
134 #define PCIINT_M_MST_ABORT 0x00000004
135 #define PCIINT_M_DPERR_WT 0x00000002
136 #define PCIINT_M_DPERR_RD 0x00000001
137 #define PCIINT_ALL 0x0000c3ff
138 #define PCIINT_CLEAR_ALL PCIINT_ALL
139
140 #define PCIINTM_MASK_ALL 0x00000000
141 #define PCIINTM_UNMASK_ALL PCIINT_ALL
142
143 #define PCIMBR_MASK 0xff000000
144
145 #define PCIIOBR_MASK 0xffc00000
146
147 #endif /* SH4_PCICREG_H */
148
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