/[gxemul]/trunk/src/include/sh4_cpu.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/sh4_cpu.h

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7157 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /* GXemul: $Id: sh4_cpu.h,v 1.2 2006/10/19 10:18:02 debug Exp $ */
2 /* $NetBSD: cpu.h,v 1.41 2006/01/21 04:24:12 uwe Exp $ */
3
4 #ifndef SH4_CPU_H
5 #define SH4_CPU_H
6
7 /*-
8 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved.
9 * Copyright (c) 1990 The Regents of the University of California.
10 * All rights reserved.
11 *
12 * This code is derived from software contributed to Berkeley by
13 * William Jolitz.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * @(#)cpu.h 5.4 (Berkeley) 5/9/91
40 */
41
42 /*
43 * SH3/SH4 support.
44 *
45 * T.Horiuchi Brains Corp. 5/22/98
46 */
47
48 #if defined(_KERNEL_OPT)
49 #include "opt_lockdebug.h"
50 #endif
51
52 #if 0
53 #include <sh3/psl.h>
54 #include <sh3/frame.h>
55 #endif
56
57 #ifdef _KERNEL
58 #include <sys/cpu_data.h>
59 struct cpu_info {
60 struct cpu_data ci_data; /* MI per-cpu data */
61 };
62
63 extern struct cpu_info cpu_info_store;
64 #define curcpu() (&cpu_info_store)
65
66 /*
67 * definitions of cpu-dependent requirements
68 * referenced in generic code
69 */
70 #define cpu_number() 0
71 /*
72 * Can't swapout u-area, (__SWAP_BROKEN)
73 * since we use P1 converted address for trapframe.
74 */
75 #define cpu_swapin(p) /* nothing */
76 #define cpu_swapout(p) panic("cpu_swapout: can't get here");
77 #define cpu_proc_fork(p1, p2) /* nothing */
78
79 /*
80 * Arguments to hardclock and gatherstats encapsulate the previous
81 * machine state in an opaque clockframe.
82 */
83 struct clockframe {
84 int spc; /* program counter at time of interrupt */
85 int ssr; /* status register at time of interrupt */
86 int ssp; /* stack pointer at time of interrupt */
87 };
88
89 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr))
90 #define CLKF_BASEPRI(cf) (((cf)->ssr & 0xf0) == 0)
91 #define CLKF_PC(cf) ((cf)->spc)
92 #define CLKF_INTR(cf) 0 /* XXX */
93
94 /*
95 * This is used during profiling to integrate system time. It can safely
96 * assume that the process is resident.
97 */
98 #define PROC_PC(p) \
99 (((struct trapframe *)(p)->p_md.md_regs)->tf_spc)
100
101 /*
102 * Preempt the current process if in interrupt from user mode,
103 * or after the current trap/syscall if in system mode.
104 */
105 #define need_resched(ci) \
106 do { \
107 want_resched = 1; \
108 if (curproc != NULL) \
109 aston(curproc); \
110 } while (/*CONSTCOND*/0)
111
112 /*
113 * Give a profiling tick to the current process when the user profiling
114 * buffer pages are invalid. On the MIPS, request an ast to send us
115 * through trap, marking the proc as needing a profiling tick.
116 */
117 #define need_proftick(p) \
118 do { \
119 (p)->p_flag |= P_OWEUPC; \
120 aston(p); \
121 } while (/*CONSTCOND*/0)
122
123 /*
124 * Notify the current process (p) that it has a signal pending,
125 * process as soon as possible.
126 */
127 #define signotify(p) aston(p)
128
129 #define aston(p) ((p)->p_md.md_astpending = 1)
130
131 extern int want_resched; /* need_resched() was called */
132
133 /*
134 * We need a machine-independent name for this.
135 */
136 #define DELAY(x) delay(x)
137 #endif /* _KERNEL */
138
139 /*
140 * Logical address space of SH3/SH4 CPU.
141 */
142 #define SH3_PHYS_MASK 0x1fffffff
143
144 #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */
145 #define SH3_P0SEG_END 0x7fffffff
146 #define SH3_P1SEG_BASE 0x80000000 /* pa == va */
147 #define SH3_P1SEG_END 0x9fffffff
148 #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */
149 #define SH3_P2SEG_END 0xbfffffff
150 #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */
151 #define SH3_P3SEG_END 0xdfffffff
152 #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */
153 #define SH3_P4SEG_END 0xffffffff
154
155 #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)
156 #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)
157 #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE)
158 #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE)
159 #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000)
160 #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000)
161
162 #ifndef __lint__
163
164 /* switch from P1 to P2 */
165 #define RUN_P2 do { \
166 void *p; \
167 p = &&P2; \
168 goto *(void *)SH3_P1SEG_TO_P2SEG(p); \
169 P2: (void)0; \
170 } while (0)
171
172 /* switch from P2 to P1 */
173 #define RUN_P1 do { \
174 void *p; \
175 p = &&P1; \
176 __asm volatile("nop;nop;nop;nop;nop;nop;nop;nop"); \
177 goto *(void *)SH3_P2SEG_TO_P1SEG(p); \
178 P1: (void)0; \
179 } while (0)
180
181 #else /* __lint__ */
182 #define RUN_P2 do {} while (/* CONSTCOND */ 0)
183 #define RUN_P1 do {} while (/* CONSTCOND */ 0)
184 #endif
185
186 /* #if defined(SH4) */
187 /* SH4 Processor Version Register */
188 #define SH4_PVR_ADDR 0xff000030 /* P4 address */
189 #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR)
190 #define SH4_PRR_ADDR 0xff000044 /* P4 address */
191 #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR)
192
193 #define SH4_PVR_MASK 0xffffff00
194 #define SH4_PVR_SH7750 0x04020500 /* SH7750 */
195 #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */
196 #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */
197 #define SH4_PVR_SH7751 0x04110000 /* SH7751 */
198
199 #define SH4_PRR_MASK 0xfffffff0
200 #define SH4_PRR_7750R 0x00000100 /* SH7750R */
201 #define SH4_PRR_7751R 0x00000110 /* SH7751R */
202 /* #endif */
203
204 /*
205 * pull in #defines for kinds of processors
206 */
207 /* #include <machine/cputypes.h> */
208
209 /*
210 * CTL_MACHDEP definitions.
211 */
212 #define CPU_CONSDEV 1 /* dev_t: console terminal device */
213 #define CPU_LOADANDRESET 2 /* load kernel image and reset */
214 #define CPU_MAXID 3 /* number of valid machdep ids */
215
216 #define CTL_MACHDEP_NAMES { \
217 { 0, 0 }, \
218 { "console_device", CTLTYPE_STRUCT }, \
219 { "load_and_reset", CTLTYPE_INT }, \
220 }
221
222 #ifdef _KERNEL
223 void sh_cpu_init(int, int);
224 void sh_startup(void);
225 void cpu_reset(void) __attribute__((__noreturn__)); /* soft reset */
226 void _cpu_spin(uint32_t); /* for delay loop. */
227 void delay(int);
228 struct pcb;
229 void savectx(struct pcb *);
230 void dumpsys(void);
231 #endif /* _KERNEL */
232
233 #endif /* SH4_CPU_H */
234

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