/[gxemul]/trunk/src/include/sgi_macereg.h
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Contents of /trunk/src/include/sgi_macereg.h

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6832 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /* GXemul: $Id: sgi_macereg.h,v 1.2 2007/01/20 16:11:26 debug Exp $ */
2 /* $NetBSD: macereg.h,v 1.2 2005/12/11 12:18:54 christos Exp $ */
3
4 #ifndef SGI_MACEREG_H
5 #define SGI_MACEREG_H
6
7 /*
8 * Copyright (c) 2000 Soren S. Jorvang
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed for the
22 * NetBSD Project. See http://www.NetBSD.org/ for
23 * information about NetBSD.
24 * 4. The name of the author may not be used to endorse or promote products
25 * derived from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #define MACE_BASE 0x1f000000
40
41 /* PCI definitions (offset 0x080000) */
42
43 #define MACE_PCI_ERROR_ADDR 0x00
44 #define MACE_PCI_ERROR_FLAGS 0x04
45
46 #define MACE_PCI_CONTROL 0x08
47 #define MACE_PCI_CONTROL_INT_MASK 0x000000ff
48 #define MACE_PCI_CONTROL_SERR_ENA 0x00000100
49 #define MACE_PCI_CONTROL_ARB_N6 0x00000200
50 #define MACE_PCI_CONTROL_PARITY_ERR 0x00000400
51 #define MACE_PCI_CONTROL_MRMRA_ENA 0x00000800
52 #define MACE_PCI_CONTROL_ARB_N3 0x00001000
53 #define MACE_PCI_CONTROL_ARB_N4 0x00002000
54 #define MACE_PCI_CONTROL_ARB_N5 0x00004000
55 #define MACE_PCI_CONTROL_PARK_LIU 0x00008000
56
57 #define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000
58 #define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000
59 #define MACE_PCI_CONTROL_PARITY_INT 0x02000000
60 #define MACE_PCI_CONTROL_SERR_INT 0x04000000
61 #define MACE_PCI_CONTROL_IT_INT 0x08000000
62 #define MACE_PCI_CONTROL_RE_INT 0x10000000
63 #define MACE_PCI_CONTROL_DPED_INT 0x20000000
64 #define MACE_PCI_CONTROL_TAR_INT 0x40000000
65 #define MACE_PCI_CONTROL_MAR_INT 0x80000000
66
67
68 #define MACE_PCI_REV_INFO_R 0x0c
69 #define MACE_PCI_FLUSH_W 0x0c
70 #define MACE_PCI_CONFIG_ADDR 0xcf8
71 #define MACE_PCI_CONFIG_DATA 0xcfc
72 #define MACE_PCI_LOW_MEMORY 0x1a000000
73 #define MACE_PCI_LOW_IO 0x18000000
74 #define MACE_PCI_NATIVE_VIEW 0x40000000
75 #define MACE_PCI_IO 0x80000000
76 #define MACE_PCI_HI_MEMORY 0x280000000
77 #define MACE_PCI_HI_IO 0x100000000
78
79 #define MACE_VIN1 0x100000
80 #define MACE_VIN2 0x180000
81 #define MACE_VOUT 0x200000
82 #define MACE_PERIF 0x300000
83 #define MACE_ISA_EXT 0x380000
84
85 #if 1
86 /* GXemul, making it easier to use offsets further down: */
87 #define MACE_AUDIO 0
88 #define MACE_ISA 0
89 #define MACE_KBDMS 0
90 #define MACE_I2C 0
91 #define MACE_UST_MSC 0
92 #else
93 #define MACE_AUDIO (MACE_PERIF + 0x00000)
94 #define MACE_ISA (MACE_PERIF + 0x10000)
95 #define MACE_KBDMS (MACE_PERIF + 0x20000)
96 #define MACE_I2C (MACE_PERIF + 0x30000)
97 #define MACE_UST_MSC (MACE_PERIF + 0x40000)
98 #endif
99
100
101 /***********************
102 * PCI_ERROR_FLAGS Bits
103 */
104 #define MACE_PERR_MASTER_ABORT 0x80000000
105 #define MACE_PERR_TARGET_ABORT 0x40000000
106 #define MACE_PERR_DATA_PARITY_ERR 0x20000000
107 #define MACE_PERR_RETRY_ERR 0x10000000
108 #define MACE_PERR_ILLEGAL_CMD 0x08000000
109 #define MACE_PERR_SYSTEM_ERR 0x04000000
110 #define MACE_PERR_INTERRUPT_TEST 0x02000000
111 #define MACE_PERR_PARITY_ERR 0x01000000
112 #define MACE_PERR_OVERRUN 0x00800000
113 #define MACE_PERR_RSVD 0x00400000
114 #define MACE_PERR_MEMORY_ADDR 0x00200000
115 #define MACE_PERR_CONFIG_ADDR 0x00100000
116 #define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000
117 #define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000
118 #define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000
119 #define MACE_PERR_RETRY_ADDR_VALID 0x00010000
120
121
122 /*******************************
123 * MACE ISA External Address Map
124 */
125 #define MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000)
126 #define MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000)
127 #define MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000)
128 #define MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000)
129 #define MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000)
130 #define MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000)
131
132
133 /*************************
134 * ISA Interface Registers
135 */
136
137 /* ISA Ringbase Address and Reset Register */
138
139 #define MACE_ISA_RINGBASE (MACE_ISA + 0x0000)
140
141 /* Flash-ROM/LED/DP-RAM/NIC Controller Register */
142
143 #define MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008)
144 #define MACE_ISA_FLASH_WE 0x01 /* 1=> Enable FLASH writes */
145 #define MACE_ISA_PWD_CLEAR 0x02 /* 1=> PWD CLEAR jumper detected */
146 #define MACE_ISA_NIC_DEASSERT 0x04
147 #define MACE_ISA_NIC_DATA 0x08
148 #define MACE_ISA_LED_RED 0x10 /* 1=> Illuminate RED LED */
149 #define MACE_ISA_LED_GREEN 0x20 /* 1=> Illuminate GREEN LED */
150 #define MACE_ISA_DP_RAM_ENABLE 0x40
151
152 /* Interrupt Status and Mask Registers (32 bits) */
153
154 #define MACE_ISA_INT_STATUS (MACE_ISA + 0x0010)
155 #define MACE_ISA_INT_MASK (MACE_ISA + 0x0018)
156
157 /* bit definitions */
158 #define MACE_ISA_INT_RTC_IRQ 0x00000100
159
160
161 /********************************
162 * MACE Timer Interface Registers
163 *
164 * Note: MSC_UST<31:0> is MSC, MSC_UST<63:32> is UST.
165 */
166 #define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */
167 #define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */
168 #define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */
169 #define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */
170 #define MACE_UST_PERIOD 960 /* UST Period in ns */
171
172 #define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */
173 #define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */
174 #define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */
175 #define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */
176 #define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */
177 #define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */
178
179 #endif /* SGI_MACEREG_H */

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