/[gxemul]/trunk/src/include/sccreg.h
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Contents of /trunk/src/include/sccreg.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 14109 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /* gxemul: $Id: sccreg.h,v 1.3 2005/03/05 12:34:03 debug Exp $ */
2
3 #ifndef SCCREG_H
4 #define SCCREG_H
5
6 /* $NetBSD: sccreg.h,v 1.6 1999/04/24 08:01:07 simonb Exp $ */
7
8 /*-
9 * Copyright (c) 1992, 1993
10 * The Regents of the University of California. All rights reserved.
11 *
12 * This code is derived from software contributed to Berkeley by
13 * Ralph Campbell and Rick Macklem.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * @(#)sccreg.h 8.1 (Berkeley) 6/10/93
44 */
45
46 /*
47 * Mach Operating System
48 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
49 * All Rights Reserved.
50 *
51 * Permission to use, copy, modify and distribute this software and its
52 * documentation is hereby granted, provided that both the copyright
53 * notice and this permission notice appear in all copies of the
54 * software, derivative works or modified versions, and any portions
55 * thereof, and that both notices appear in supporting documentation.
56 *
57 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
58 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
59 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
60 *
61 * Carnegie Mellon requests users of this software to return to
62 *
63 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
64 * School of Computer Science
65 * Carnegie Mellon University
66 * Pittsburgh PA 15213-3890
67 *
68 * any improvements or extensions that they make and grant Carnegie Mellon
69 * the rights to redistribute these changes.
70 */
71 /*
72 * Definitions for Intel 82530 serial communications chip.
73 * Each chip is a dual uart with the A channels used for the keyboard and
74 * mouse with the B channel(s) for comm ports with modem control. Since
75 * some registers are used for the other channel, the following macros
76 * are used to access the register ports.
77 */
78 typedef struct scc_regmap {
79 /* Channel B is first, then A */
80 struct {
81 char scc_pad0;
82 volatile u_char scc_command; /* reg select */
83 char scc_pad1[3];
84 volatile u_char scc_data; /* Rx/Tx buffer */
85 char scc_pad3[2];
86 } scc_channel[2];
87 } scc_regmap_t;
88
89 #define SCC_CHANNEL_A 1
90 #define SCC_CHANNEL_B 0
91
92 #define SCC_INIT_REG(scc,chan) { \
93 char tmp; \
94 tmp = (scc)->scc_channel[(chan)].scc_command; \
95 tmp = (scc)->scc_channel[(chan)].scc_command; \
96 }
97
98 #define SCC_READ_REG(scc,chan,reg,val) { \
99 (scc)->scc_channel[(chan)].scc_command = (reg); \
100 (val) = (scc)->scc_channel[(chan)].scc_command; \
101 }
102
103 #define SCC_READ_REG_ZERO(scc,chan,val) { \
104 (val) = (scc)->scc_channel[(chan)].scc_command; \
105 }
106
107 #define SCC_WRITE_REG(scc,chan,reg,val) { \
108 (scc)->scc_channel[(chan)].scc_command = (reg); \
109 (scc)->scc_channel[(chan)].scc_command = (val); \
110 }
111
112 #define SCC_WRITE_REG_ZERO(scc,chan,val) { \
113 (scc)->scc_channel[(chan)].scc_command = (val); \
114 }
115
116 #define SCC_READ_DATA(scc,chan,val) { \
117 (val) = (scc)->scc_channel[(chan)].scc_data; \
118 }
119
120 #define SCC_WRITE_DATA(scc,chan,val) { \
121 (scc)->scc_channel[(chan)].scc_data = (val); \
122 }
123
124 #define SCC_RR0 0 /* status register */
125 #define SCC_RR1 1 /* special receive conditions */
126 #define SCC_RR2 2 /* (modified) interrupt vector */
127 #define SCC_RR3 3 /* interrupts pending (cha A only) */
128 #define SCC_RR8 8 /* recv buffer (alias for data) */
129 #define SCC_RR10 10 /* sdlc status */
130 #define SCC_RR12 12 /* BRG constant, low part */
131 #define SCC_RR13 13 /* BRG constant, high part */
132 #define SCC_RR15 15 /* interrupts currently enabled */
133
134 #define SCC_WR0 0 /* reg select, and commands */
135 #define SCC_WR1 1 /* interrupt and DMA enables */
136 #define SCC_WR2 2 /* interrupt vector */
137 #define SCC_WR3 3 /* receiver params and enables */
138 #define SCC_WR4 4 /* clock/char/parity params */
139 #define SCC_WR5 5 /* xmit params and enables */
140 #define SCC_WR6 6 /* synchr SYNCH/address */
141 #define SCC_WR7 7 /* synchr SYNCH/flag */
142 #define SCC_WR8 8 /* xmit buffer (alias for data) */
143 #define SCC_WR9 9 /* vectoring and resets */
144 #define SCC_WR10 10 /* synchr params */
145 #define SCC_WR11 11 /* clocking definitions */
146 #define SCC_WR12 12 /* BRG constant, low part */
147 #define SCC_WR13 13 /* BRG constant, high part */
148 #define SCC_WR14 14 /* BRG enables and commands */
149 #define SCC_WR15 15 /* interrupt enables */
150
151 /*
152 * Read registers defines
153 */
154 #define SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */
155 #define SCC_RR0_ABORT 0x80 /* abort (synchr) */
156 #define SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */
157 #define SCC_RR0_CTS 0x20 /* clear-to-send pin active (sampled
158 only on intr and after RESI cmd */
159 #define SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */
160 #define SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */
161 #define SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */
162 #define SCC_RR0_ZERO_COUNT 0x02 /* ? */
163 #define SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */
164
165 #define SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */
166 #define SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */
167 #define SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */
168 #define SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */
169 #define SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */
170 #define SCC_RR1_RESIDUE0 0x08
171 #define SCC_RR1_RESIDUE1 0x04
172 #define SCC_RR1_RESIDUE2 0x02
173 #define SCC_RR1_ALL_SENT 0x01
174
175 /* RR2 contains the interrupt vector unmodified (channel A) or
176 modified as follows (channel B, if vector-include-status) */
177
178 #define SCC_RR2_STATUS(val) ((val)&0xf)
179
180 #define SCC_RR2_B_XMIT_DONE 0x0
181 #define SCC_RR2_B_EXT_STATUS 0x2
182 #define SCC_RR2_B_RECV_DONE 0x4
183 #define SCC_RR2_B_RECV_SPECIAL 0x6
184 #define SCC_RR2_A_XMIT_DONE 0x8
185 #define SCC_RR2_A_EXT_STATUS 0xa
186 #define SCC_RR2_A_RECV_DONE 0xc
187 #define SCC_RR2_A_RECV_SPECIAL 0xe
188
189 /* Interrupts pending, to be read from channel A only (B raz) */
190 #define SCC_RR3_zero 0xc0
191 #define SCC_RR3_RX_IP_A 0x20
192 #define SCC_RR3_TX_IP_A 0x10
193 #define SCC_RR3_EXT_IP_A 0x08
194 #define SCC_RR3_RX_IP_B 0x04
195 #define SCC_RR3_TX_IP_B 0x02
196 #define SCC_RR3_EXT_IP_B 0x01
197
198 /* RR8 is the receive data buffer, a 3 deep FIFO */
199 #define SCC_RECV_BUFFER SCC_RR8
200 #define SCC_RECV_FIFO_DEEP 3
201
202 #define SCC_RR10_1CLKS 0x80
203 #define SCC_RR10_2CLKS 0x40
204 #define SCC_RR10_zero 0x2d
205 #define SCC_RR10_LOOP_SND 0x10
206 #define SCC_RR10_ON_LOOP 0x02
207
208 /* RR12/RR13 hold the timing base, upper byte in RR13 */
209
210 #define SCC_GET_TIMING_BASE(scc,chan,val) { \
211 char tmp; \
212 SCC_READ_REG(scc,chan,SCC_RR12,val);\
213 SCC_READ_REG(scc,chan,SCC_RR13,tmp);\
214 (val) = ((val)<<8)|(tmp&0xff);\
215 }
216
217 #define SCC_RR15_BREAK_IE 0x80
218 #define SCC_RR15_TX_UNDERRUN_IE 0x40
219 #define SCC_RR15_CTS_IE 0x20
220 #define SCC_RR15_SYNCH_IE 0x10
221 #define SCC_RR15_DCD_IE 0x08
222 #define SCC_RR15_zero 0x05
223 #define SCC_RR15_ZERO_COUNT_IE 0x02
224
225 /*
226 * Write registers defines
227 */
228 /* WR0 is used for commands too */
229 #define SCC_RESET_TXURUN_LATCH 0xc0
230 #define SCC_RESET_TX_CRC 0x80
231 #define SCC_RESET_RX_CRC 0x40
232 #define SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */
233 #define SCC_RESET_ERROR 0x30
234 #define SCC_RESET_TX_IP 0x28
235 #define SCC_IE_NEXT_CHAR 0x20
236 #define SCC_SEND_SDLC_ABORT 0x18
237 #define SCC_RESET_EXT_IP 0x10
238
239 #define SCC_WR1_DMA_ENABLE 0x80 /* dma control */
240 #define SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */
241 #define SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */
242 /* interrupt enable/conditions */
243 #define SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */
244 #define SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */
245 #define SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */
246 #define SCC_WR1_RXI_DISABLE 0x00 /* never on recv */
247 #define SCC_WR1_PARITY_IE 0x04 /* on parity errors */
248 #define SCC_WR1_TX_IE 0x02
249 #define SCC_WR1_EXT_IE 0x01
250
251 /* WR2 is common and contains the interrupt vector (high nibble) */
252
253 #define SCC_WR3_RX_8_BITS 0xc0
254 #define SCC_WR3_RX_6_BITS 0x80
255 #define SCC_WR3_RX_7_BITS 0x40
256 #define SCC_WR3_RX_5_BITS 0x00
257 #define SCC_WR3_AUTO_ENABLE 0x20
258 #define SCC_WR3_HUNT_MODE 0x10
259 #define SCC_WR3_RX_CRC_ENABLE 0x08
260 #define SCC_WR3_SDLC_SRCH 0x04
261 #define SCC_WR3_INHIBIT_SYNCH 0x02
262 #define SCC_WR3_RX_ENABLE 0x01
263
264 /* Should be re-written after reset */
265 #define SCC_WR4_CLK_x64 0xc0 /* clock divide factor */
266 #define SCC_WR4_CLK_x32 0x80
267 #define SCC_WR4_CLK_x16 0x40
268 #define SCC_WR4_CLK_x1 0x00
269 #define SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */
270 #define SCC_WR4_SDLC_MODE 0x20
271 #define SCC_WR4_16BIT_SYNCH 0x10
272 #define SCC_WR4_8BIT_SYNCH 0x00
273 #define SCC_WR4_2_STOP 0x0c /* asynch modes */
274 #define SCC_WR4_1_5_STOP 0x08
275 #define SCC_WR4_1_STOP 0x04
276 #define SCC_WR4_SYNCH_MODE 0x00
277 #define SCC_WR4_EVEN_PARITY 0x02
278 #define SCC_WR4_PARITY_ENABLE 0x01
279
280 #define SCC_WR5_DTR 0x80 /* drive DTR pin */
281 #define SCC_WR5_TX_8_BITS 0x60
282 #define SCC_WR5_TX_6_BITS 0x40
283 #define SCC_WR5_TX_7_BITS 0x20
284 #define SCC_WR5_TX_5_BITS 0x00
285 #define SCC_WR5_SEND_BREAK 0x10
286 #define SCC_WR5_TX_ENABLE 0x08
287 #define SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */
288 #define SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */
289 #define SCC_WR5_RTS 0x02 /* drive RTS pin */
290 #define SCC_WR5_TX_CRC_ENABLE 0x01
291
292 /* Registers WR6 and WR7 are for synch modes data, with among other things: */
293
294 #define SCC_WR6_BISYNCH_12 0x0f
295 #define SCC_WR6_SDLC_RANGE_MASK 0x0f
296 #define SCC_WR7_SDLC_FLAG 0x7e
297
298 /* WR8 is the transmit data buffer (no FIFO) */
299 #define SCC_XMT_BUFFER SCC_WR8
300
301 #define SCC_WR9_HW_RESET 0xc0 /* force hardware reset */
302 #define SCC_WR9_RESET_CHA_A 0x80
303 #define SCC_WR9_RESET_CHA_B 0x40
304 #define SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */
305 #define SCC_WR9_STATUS_HIGH 0x10
306 #define SCC_WR9_MASTER_IE 0x08
307 #define SCC_WR9_DLC 0x04 /* disable-lower-chain */
308 #define SCC_WR9_NV 0x02 /* no vector */
309 #define SCC_WR9_VIS 0x01 /* vector-includes-status */
310
311 #define SCC_WR10_CRC_PRESET 0x80
312 #define SCC_WR10_FM0 0x60
313 #define SCC_WR10_FM1 0x40
314 #define SCC_WR10_NRZI 0x20
315 #define SCC_WR10_NRZ 0x00
316 #define SCC_WR10_ACTIVE_ON_POLL 0x10
317 #define SCC_WR10_MARK_IDLE 0x08 /* flag if zero */
318 #define SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */
319 #define SCC_WR10_LOOP_MODE 0x02
320 #define SCC_WR10_6BIT_SYNCH 0x01
321 #define SCC_WR10_8BIT_SYNCH 0x00
322
323 #define SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */
324 #define SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */
325 #define SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */
326 #define SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */
327 #define SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */
328 #define SCC_WR11_XTLK_DPLL 0x18
329 #define SCC_WR11_XTLK_BAUDR 0x10
330 #define SCC_WR11_XTLK_TRc_PIN 0x08
331 #define SCC_WR11_XTLK_RTc_PIN 0x00
332 #define SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/
333 #define SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */
334 #define SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */
335 #define SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */
336 #define SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */
337
338 /* WR12/WR13 are for timing base preset */
339 #define SCC_SET_TIMING_BASE(scc,chan,val) { \
340 SCC_WRITE_REG(scc,chan,SCC_RR12,val);\
341 SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\
342 }
343
344 /* More commands in this register */
345 #define SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */
346 #define SCC_WR14_FM_MODE 0xc0
347 #define SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */
348 #define SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */
349 #define SCC_WR14_DISABLE_DPLL 0x60
350 #define SCC_WR14_RESET_CLKMISS 0x40
351 #define SCC_WR14_SEARCH_MODE 0x20
352 /* ..and more bitsy */
353 #define SCC_WR14_LOCAL_LOOPB 0x10
354 #define SCC_WR14_AUTO_ECHO 0x08
355 #define SCC_WR14_DTR_REQUEST 0x04
356 #define SCC_WR14_BAUDR_SRC 0x02
357 #define SCC_WR14_BAUDR_ENABLE 0x01
358
359 #define SCC_WR15_BREAK_IE 0x80
360 #define SCC_WR15_TX_UNDERRUN_IE 0x40
361 #define SCC_WR15_CTS_IE 0x20
362 #define SCC_WR15_SYNCHUNT_IE 0x10
363 #define SCC_WR15_DCD_IE 0x08
364 #define SCC_WR15_zero 0x05
365 #define SCC_WR15_ZERO_COUNT_IE 0x02
366
367 /* bits in dm lsr, copied from dmreg.h */
368 #define DML_DSR 0000400 /* data set ready, not a real DM bit */
369 #define DML_RNG 0000200 /* ring */
370 #define DML_CAR 0000100 /* carrier detect */
371 #define DML_CTS 0000040 /* clear to send */
372 #define DML_SR 0000020 /* secondary receive */
373 #define DML_ST 0000010 /* secondary transmit */
374 #define DML_RTS 0000004 /* request to send */
375 #define DML_DTR 0000002 /* data terminal ready */
376 #define DML_LE 0000001 /* line enable */
377
378 /*
379 * Minor device numbers for scc. Weird because B channel comes
380 * first and the A channels are wired for keyboard/mouse and the
381 * B channels for the comm port(s).
382 */
383 #define SCCCOMM2_PORT 0x0
384 #define SCCMOUSE_PORT 0x1
385 #define SCCCOMM3_PORT 0x2
386 #define SCCKBD_PORT 0x3
387
388 #endif /* SCCREG_H */

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