44 |
#define SANDPOINT_SDRAM_BASE 0x00000000 |
#define SANDPOINT_SDRAM_BASE 0x00000000 |
45 |
|
|
46 |
/* Flash */ |
/* Flash */ |
47 |
#define SANDPOINT_FLASH_BASE 0x70000000 |
#define SANDPOINT_FLASH_BASE 0xffc00000 |
48 |
|
|
49 |
#define SANDPOINT_IO_START 0x7fe00000 |
#if 0 |
50 |
|
#define SANDPOINT_IO_START 0xfc000000 |
51 |
|
|
52 |
/* CS8900A ethernet */ |
/* CS8900A ethernet */ |
53 |
#define SANDPOINT_CS_IO_BASE 0x7fe00000 |
#define SANDPOINT_CS_IO_BASE 0x7fe00000 |
57 |
/* time-of-day clock */ |
/* time-of-day clock */ |
58 |
#define SANDPOINT_RTC 0x7ff00000 |
#define SANDPOINT_RTC 0x7ff00000 |
59 |
#define SANDPOINT_RTC_SIZE 0x00002000 |
#define SANDPOINT_RTC_SIZE 0x00002000 |
60 |
|
#endif |
61 |
|
|
62 |
/* board config regs */ |
/* board config regs */ |
63 |
#define SANDPOINT_CONFIG0 0x7ff40000 |
#define SANDPOINT_CONFIG0 0x7ff40000 |
68 |
#define SANDPOINT_RESET_SEQ_STEP2 0x1d |
#define SANDPOINT_RESET_SEQ_STEP2 0x1d |
69 |
#define SANDPOINT_INTR 0x7ff40004 |
#define SANDPOINT_INTR 0x7ff40004 |
70 |
|
|
71 |
|
#if 0 |
72 |
/* ROM */ |
/* ROM */ |
73 |
#define SANDPOINT_ROM_BASE 0x7ff80000 |
#define SANDPOINT_ROM_BASE 0x7ff80000 |
74 |
|
|
79 |
#define SANDPOINT_I_BPMC_INTB CPC_IB_EXT1 /* PCI INTB */ |
#define SANDPOINT_I_BPMC_INTB CPC_IB_EXT1 /* PCI INTB */ |
80 |
#define SANDPOINT_I_BPMC_INTC CPC_IB_EXT2 /* PCI INTC */ |
#define SANDPOINT_I_BPMC_INTC CPC_IB_EXT2 /* PCI INTC */ |
81 |
#define SANDPOINT_I_BPMC_INTD CPC_IB_EXT3 /* PCI INTD */ |
#define SANDPOINT_I_BPMC_INTD CPC_IB_EXT3 /* PCI INTD */ |
82 |
#define SANDPOINT_I_ETH_INT CPC_IB_EXT4 /* ethernet */ |
#define SANDPOINT_I_ETH_INT CPC_IB_EXT4 /* ethernet */ |
83 |
#define SANDPOINT_I_RTC_INT CPC_IB_EXT5 /* rtc */ |
#define SANDPOINT_I_RTC_INT CPC_IB_EXT5 /* rtc */ |
84 |
|
|
85 |
|
#endif |
86 |
|
|
87 |
/* |
/* |
88 |
* The variables below are extracted from the config register located |
* The variables below are extracted from the config register located |