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/* gxemul: $Id: ps2_dmacreg.h,v 1.4 2005/03/05 12:34:03 debug Exp $ */ |
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|
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#ifndef PS2_DMACREG_H |
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#define PS2_DMACREG_H |
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|
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/* gxemul: MIPS_PHYS_TO_KSEG1 has been changed to PS2_PHYS_TO_KSEG1. */ |
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#define PS2_PHYS_TO_KSEG1(x) (x - 0x10008000) |
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|
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/* $NetBSD: dmacreg.h,v 1.1 2001/10/16 15:38:36 uch Exp $ */ |
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|
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/*- |
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* Copyright (c) 2001 The NetBSD Foundation, Inc. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to The NetBSD Foundation |
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* by UCHIYAMA Yasushi. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the NetBSD |
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* Foundation, Inc. and its contributors. |
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* 4. Neither the name of The NetBSD Foundation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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typedef uint64_t dmatag_t; |
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|
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#define DMAC_BLOCK_SIZE 16 |
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#define DMAC_SLICE_SIZE 128 |
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#define DMAC_TRANSFER_QWCMAX 0xffff |
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|
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/* all register length are 32bit */ |
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#define DMAC_REGBASE PS2_PHYS_TO_KSEG1(0x10008000) |
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#define DMAC_REGSIZE 0x00010000 |
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|
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/* |
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* DMAC common registers. |
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*/ |
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#define D_CTRL_REG PS2_PHYS_TO_KSEG1(0x1000e000) /* DMA control */ |
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#define D_STAT_REG PS2_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */ |
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#define D_PCR_REG PS2_PHYS_TO_KSEG1(0x1000e020) /* priority control */ |
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#define D_SQWC_REG PS2_PHYS_TO_KSEG1(0x1000e030) /* interleave size */ |
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#define D_RBOR_REG PS2_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */ |
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#define D_RBSR_REG PS2_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */ |
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#define D_STADR_REG PS2_PHYS_TO_KSEG1(0x1000e060) /* stall address */ |
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#define D_ENABLER_REG PS2_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */ |
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#define D_ENABLEW_REG PS2_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */ |
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|
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/* |
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* Channel registers. (10ch) |
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*/ |
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#define DMA_CH_VIF0 0 /* to (priority 0) */ |
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#define DMA_CH_VIF1 1 /* both */ |
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#define DMA_CH_GIF 2 /* to */ |
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#define DMA_CH_FROMIPU 3 |
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#define DMA_CH_TOIPU 4 |
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#define DMA_CH_SIF0 5 /* from */ |
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#define DMA_CH_SIF1 6 /* to */ |
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#define DMA_CH_SIF2 7 /* both (priority 1) */ |
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#define DMA_CH_FROMSPR 8 /* burst channel */ |
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#define DMA_CH_TOSPR 9 /* burst channel */ |
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#define DMA_CH_VALID(x) (((x) >= 0) && ((x) <= 9)) |
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|
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#define D_CHCR_OFS 0x00 |
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#define D_MADR_OFS 0x10 |
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#define D_QWC_OFS 0x20 |
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#define D_TADR_OFS 0x30 |
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#define D_ASR0_OFS 0x40 |
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#define D_ASR1_OFS 0x50 |
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#define D_SADR_OFS 0x80 |
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|
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#define D0_REGBASE PS2_PHYS_TO_KSEG1(0x10008000) |
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#define D1_REGBASE PS2_PHYS_TO_KSEG1(0x10009000) |
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#define D2_REGBASE PS2_PHYS_TO_KSEG1(0x1000a000) |
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#define D3_REGBASE PS2_PHYS_TO_KSEG1(0x1000b000) |
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#define D4_REGBASE PS2_PHYS_TO_KSEG1(0x1000b400) |
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#define D5_REGBASE PS2_PHYS_TO_KSEG1(0x1000c000) |
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#define D6_REGBASE PS2_PHYS_TO_KSEG1(0x1000c400) |
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#define D7_REGBASE PS2_PHYS_TO_KSEG1(0x1000c800) |
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#define D8_REGBASE PS2_PHYS_TO_KSEG1(0x1000d000) |
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#define D9_REGBASE PS2_PHYS_TO_KSEG1(0x1000d400) |
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|
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#define D_CHCR_REG(base) (base) |
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#define D_MADR_REG(base) (base + D_MADR_OFS) |
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#define D_QWC_REG(base) (base + D_QWC_OFS) |
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#define D_TADR_REG(base) (base + D_TADR_OFS) |
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#define D_ASR0_REG(base) (base + D_ASR0_OFS) |
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#define D_ASR1_REG(base) (base + D_ASR1_OFS) |
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#define D_SADR_REG(base) (base + D_SADR_OFS) |
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|
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#define D0_CHCR_REG PS2_PHYS_TO_KSEG1(0x10008000) |
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#define D0_MADR_REG PS2_PHYS_TO_KSEG1(0x10008010) |
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#define D0_QWC_REG PS2_PHYS_TO_KSEG1(0x10008020) |
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#define D0_TADR_REG PS2_PHYS_TO_KSEG1(0x10008030) |
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#define D0_ASR0_REG PS2_PHYS_TO_KSEG1(0x10008040) |
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#define D0_ASR1_REG PS2_PHYS_TO_KSEG1(0x10008050) |
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|
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#define D1_CHCR_REG PS2_PHYS_TO_KSEG1(0x10009000) |
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#define D1_MADR_REG PS2_PHYS_TO_KSEG1(0x10009010) |
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#define D1_QWC_REG PS2_PHYS_TO_KSEG1(0x10009020) |
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#define D1_TADR_REG PS2_PHYS_TO_KSEG1(0x10009030) |
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#define D1_ASR0_REG PS2_PHYS_TO_KSEG1(0x10009040) |
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#define D1_ASR1_REG PS2_PHYS_TO_KSEG1(0x10009050) |
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|
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#define D2_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000a000) |
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#define D2_MADR_REG PS2_PHYS_TO_KSEG1(0x1000a010) |
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#define D2_QWC_REG PS2_PHYS_TO_KSEG1(0x1000a020) |
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#define D2_TADR_REG PS2_PHYS_TO_KSEG1(0x1000a030) |
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#define D2_ASR0_REG PS2_PHYS_TO_KSEG1(0x1000a040) |
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#define D2_ASR1_REG PS2_PHYS_TO_KSEG1(0x1000a050) |
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|
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#define D3_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000b000) |
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#define D3_MADR_REG PS2_PHYS_TO_KSEG1(0x1000b010) |
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#define D3_QWC_REG PS2_PHYS_TO_KSEG1(0x1000b020) |
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|
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#define D4_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000b400) |
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#define D4_MADR_REG PS2_PHYS_TO_KSEG1(0x1000b410) |
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#define D4_QWC_REG PS2_PHYS_TO_KSEG1(0x1000b420) |
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#define D4_TADR_REG PS2_PHYS_TO_KSEG1(0x1000b430) |
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|
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#define D5_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000c000) |
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#define D5_MADR_REG PS2_PHYS_TO_KSEG1(0x1000c010) |
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#define D5_QWC_REG PS2_PHYS_TO_KSEG1(0x1000c020) |
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|
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#define D6_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000c400) |
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#define D6_MADR_REG PS2_PHYS_TO_KSEG1(0x1000c410) |
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#define D6_QWC_REG PS2_PHYS_TO_KSEG1(0x1000c420) |
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#define D6_TADR_REG PS2_PHYS_TO_KSEG1(0x1000c430) |
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|
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#define D7_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000c800) |
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#define D7_MADR_REG PS2_PHYS_TO_KSEG1(0x1000c810) |
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#define D7_QWC_REG PS2_PHYS_TO_KSEG1(0x1000c820) |
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|
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#define D8_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000d000) |
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#define D8_MADR_REG PS2_PHYS_TO_KSEG1(0x1000d010) |
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#define D8_QWC_REG PS2_PHYS_TO_KSEG1(0x1000d020) |
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#define D8_SADR_REG PS2_PHYS_TO_KSEG1(0x1000d080) |
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|
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#define D9_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000d400) |
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#define D9_MADR_REG PS2_PHYS_TO_KSEG1(0x1000d410) |
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#define D9_QWC_REG PS2_PHYS_TO_KSEG1(0x1000d420) |
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#define D9_TADR_REG PS2_PHYS_TO_KSEG1(0x1000d430) |
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#define D9_SADR_REG PS2_PHYS_TO_KSEG1(0x1000d480) |
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|
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/* |
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* DMA control |
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*/ |
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#define D_CTRL_DMAE 0x00000001 /* all DMA enable/disable */ |
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#define D_CTRL_RELE 0x00000002 /* Cycle stealing on/off */ |
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/* Memory FIFO drain control */ |
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#define D_CTRL_MFD_MASK 0x3 |
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#define D_CTRL_MFD_SHIFT 2 |
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#define D_CTRL_MFD(x) \ |
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(((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK) |
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#define D_CTRL_MFD_CLR(x) \ |
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((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT)) |
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#define D_CTRL_MFD_SET(x, val) \ |
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((x) | (((val) << D_CTRL_MFD_SHIFT) & \ |
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(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))) |
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#define D_CTRL_MFD_DISABLE 0 |
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#define D_CTRL_MFD_VIF1 2 |
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#define D_CTRL_MFD_GIF 3 |
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|
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/* Stall control source channel */ |
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#define D_CTRL_STS_MASK 0x3 |
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#define D_CTRL_STS_SHIFT 4 |
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#define D_CTRL_STS(x) \ |
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(((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK) |
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#define D_CTRL_STS_CLR(x) \ |
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((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT)) |
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#define D_CTRL_STS_SET(x, val) \ |
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((x) | (((val) << D_CTRL_STS_SHIFT) & \ |
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(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))) |
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#define D_CTRL_STS_NONE 0 |
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#define D_CTRL_STS_SIF0 1 |
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#define D_CTRL_STS_FROMSPR 2 |
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#define D_CTRL_STS_FROMIPU 3 |
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|
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/* Stall control drain channel */ |
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#define D_CTRL_STD_MASK 0x3 |
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#define D_CTRL_STD_SHIFT 6 |
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#define D_CTRL_STD(x) \ |
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(((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK) |
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#define D_CTRL_STD_CLR(x) \ |
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((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT)) |
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#define D_CTRL_STD_SET(x, val) \ |
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((x) | (((val) << D_CTRL_STD_SHIFT) & \ |
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(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))) |
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#define D_CTRL_STD_NONE 0 |
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#define D_CTRL_STD_VIF1 1 |
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#define D_CTRL_STD_GIF 2 |
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#define D_CTRL_STD_SIF1 3 |
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|
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/* |
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* Release cycle |
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* for burst channel Cycle steanling on mode only. |
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*/ |
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#define D_CTRL_RCYC_MASK 0x7 |
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#define D_CTRL_RCYC_SHIFT 8 |
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#define D_CTRL_RCYC(x) \ |
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(((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK) |
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#define D_CTRL_RCYC_CLR(x) \ |
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((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT)) |
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#define D_CTRL_RCYC_SET(x, val) \ |
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((x) | (((val) << D_CTRL_RCYC_SHIFT) & \ |
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(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))) |
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#define D_CTRL_RCYC_CYCLE(x) (8 << (x)) |
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|
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/* |
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* Interrupt status register (write clear/invert) |
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* DMAC interrupt line connected to MIPS HwINT1 |
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*/ |
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/* MFIFO empty interrupt enable */ |
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#define D_STAT_MEIM 0x40000000 |
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/* DMA stall interrupt enable */ |
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#define D_STAT_SIM 0x20000000 |
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/* Channel interrupt enable */ |
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#define D_STAT_CIM_MASK 0x3ff |
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#define D_STAT_CIM_SHIFT 16 |
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#define D_STAT_CIM(x) (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK) |
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#define D_STAT_CIM_BIT(x) ((1 << (x)) << D_STAT_CIM_SHIFT) |
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#define D_STAT_CIM9 0x02000000 |
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#define D_STAT_CIM8 0x01000000 |
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#define D_STAT_CIM7 0x00800000 |
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#define D_STAT_CIM6 0x00400000 |
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#define D_STAT_CIM5 0x00200000 |
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#define D_STAT_CIM4 0x00100000 |
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#define D_STAT_CIM3 0x00080000 |
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#define D_STAT_CIM2 0x00040000 |
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#define D_STAT_CIM1 0x00020000 |
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#define D_STAT_CIM0 0x00010000 |
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/* BUSERR interrupt status */ |
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#define D_STAT_BEIS 0x00008000 |
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/* MFIFO empty interrupt status */ |
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#define D_STAT_MEIS 0x00004000 |
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/* DMA stall interrupt status */ |
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#define D_STAT_SIS 0x00002000 |
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/* Channel interrupt status */ |
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#define D_STAT_CIS_MASK 0x3ff |
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#define D_STAT_CIS_SHIFT 0 |
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#define D_STAT_CIS_BIT(x) (1 << (x)) |
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#define D_STAT_CIS9 0x00000200 |
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#define D_STAT_CIS8 0x00000100 |
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#define D_STAT_CIS7 0x00000080 |
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#define D_STAT_CIS6 0x00000040 |
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#define D_STAT_CIS5 0x00000020 |
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#define D_STAT_CIS4 0x00000010 |
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#define D_STAT_CIS3 0x00000008 |
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#define D_STAT_CIS2 0x00000004 |
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#define D_STAT_CIS1 0x00000002 |
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#define D_STAT_CIS0 0x00000001 |
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|
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/* |
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* Priority control register. |
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*/ |
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/* Priority control enable */ |
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#define D_PCR_PCE 0x80000000 |
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/* Channel DMA enable (packet priority control enable) */ |
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#define D_PCR_CDE_MASK 0x3ff |
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#define D_PCR_CDE_SHIFT 16 |
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#define D_PCR_CDE(x) \ |
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(((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK) |
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#define D_PCR_CDE_CLR(x) \ |
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((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT)) |
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#define D_PCR_CDE_SET(x, val) \ |
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((x) | (((val) << D_PCR_CDE_SHIFT) & \ |
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(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))) |
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#define D_PCR_CDE9 0x02000000 |
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#define D_PCR_CDE8 0x01000000 |
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#define D_PCR_CDE7 0x00800000 |
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#define D_PCR_CDE6 0x00400000 |
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#define D_PCR_CDE5 0x00200000 |
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#define D_PCR_CDE4 0x00100000 |
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#define D_PCR_CDE3 0x00080000 |
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#define D_PCR_CDE2 0x00040000 |
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#define D_PCR_CDE1 0x00020000 |
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#define D_PCR_CDE0 0x00010000 |
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/* COP control (interrupt status connect to CPCOND[0] or not) */ |
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#define D_PCR_CPC_MASK 0x3ff |
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#define D_PCR_CPC_SHIFT 0 |
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#define D_PCR_CPC(x) ((x) & D_PCR_CPC_MASK) |
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#define D_PCR_CPC_CLR(x) ((x) & ~D_PCR_CPC_MASK) |
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#define D_PCR_CPC_SET(x, val) ((x) | ((val) & D_PCR_CPC_MASK)) |
305 |
#define D_PCR_CPC_BIT(x) (1 << (x)) |
306 |
#define D_PCR_CPC9 0x00000200 |
307 |
#define D_PCR_CPC8 0x00000100 |
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#define D_PCR_CPC7 0x00000080 |
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#define D_PCR_CPC6 0x00000040 |
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#define D_PCR_CPC5 0x00000020 |
311 |
#define D_PCR_CPC4 0x00000010 |
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#define D_PCR_CPC3 0x00000008 |
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#define D_PCR_CPC2 0x00000004 |
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#define D_PCR_CPC1 0x00000002 |
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#define D_PCR_CPC0 0x00000001 |
316 |
|
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/* |
318 |
* Interleave size register |
319 |
*/ |
320 |
/* Transfer quadword counter */ |
321 |
#define D_SQWC_TQWC_MASK 0xff |
322 |
#define D_SQWC_TQWC_SHIFT 16 |
323 |
#define D_SQWC_TQWC(x) \ |
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(((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK) |
325 |
#define D_SQWC_TQWC_CLR(x) \ |
326 |
((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT)) |
327 |
#define D_SQWC_TQWC_SET(x, val) \ |
328 |
((x) | (((val) << D_SQWC_TQWC_SHIFT) & \ |
329 |
(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))) |
330 |
/* Skip quadword counter */ |
331 |
#define D_SQWC_SQWC_MASK 0xff |
332 |
#define D_SQWC_SQWC_SHIFT 0 |
333 |
#define D_SQWC_SQWC(x) \ |
334 |
(((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK) |
335 |
#define D_SQWC_SQWC_CLR(x) \ |
336 |
((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT)) |
337 |
#define D_SQWC_SQWC_SET(x, val) \ |
338 |
((x) | (((val) << D_SQWC_SQWC_SHIFT) & \ |
339 |
(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))) |
340 |
|
341 |
/* |
342 |
* Ring buffer address register |
343 |
* 16byte alignment address [30:4] |
344 |
*/ |
345 |
|
346 |
/* |
347 |
* Ring buffer size register |
348 |
* must be 2 ** n qword. [30:4] |
349 |
*/ |
350 |
|
351 |
/* |
352 |
* Stall address register |
353 |
* [30:0] (qword alignment) |
354 |
*/ |
355 |
|
356 |
/* |
357 |
* DMA suspend register |
358 |
*/ |
359 |
#define D_ENABLE_SUSPEND 0x00010000 |
360 |
|
361 |
|
362 |
/* |
363 |
* Channel specific register. |
364 |
*/ |
365 |
|
366 |
/* CHANNEL CONTROL REGISTER */ |
367 |
/* upper 16bit of DMA tag last read. */ |
368 |
#define D_CHCR_TAG_MASK 0xff |
369 |
#define D_CHCR_TAG_SHIFT 16 |
370 |
#define D_CHCR_TAG(x) \ |
371 |
(((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK) |
372 |
#define D_CHCR_TAG_CLR(x) \ |
373 |
((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT)) |
374 |
#define D_CHCR_TAG_SET(x, val) \ |
375 |
((x) | (((val) << D_CHCR_TAG_SHIFT) & \ |
376 |
(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))) |
377 |
/* DMA start */ |
378 |
#define D_CHCR_STR 0x00000100 |
379 |
/* Tag interrupt enable (IRQ bit of DMAtag) */ |
380 |
#define D_CHCR_TIE 0x00000080 |
381 |
/* Tag transfer enable (Source chain mode only) */ |
382 |
#define D_CHCR_TTE 0x00000040 |
383 |
/* Address stack pointer */ |
384 |
#define D_CHCR_ASP_MASK 0x3 |
385 |
#define D_CHCR_ASP_SHIFT 4 |
386 |
#define D_CHCR_ASP(x) \ |
387 |
(((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK) |
388 |
#define D_CHCR_ASP_CLR(x) \ |
389 |
((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT)) |
390 |
#define D_CHCR_ASP_SET(x, val) \ |
391 |
((x) | (((val) << D_CHCR_ASP_SHIFT) & \ |
392 |
(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))) |
393 |
#define D_CHCR_ASP_PUSHED_NONE 0 |
394 |
#define D_CHCR_ASP_PUSHED_1 1 |
395 |
#define D_CHCR_ASP_PUSHED_2 2 |
396 |
/* Logical transfer mode */ |
397 |
#define D_CHCR_MOD_MASK 0x3 |
398 |
#define D_CHCR_MOD_SHIFT 2 |
399 |
#define D_CHCR_MOD(x) \ |
400 |
(((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK) |
401 |
#define D_CHCR_MOD_CLR(x) \ |
402 |
((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT)) |
403 |
#define D_CHCR_MOD_SET(x, val) \ |
404 |
((x) | (((val) << D_CHCR_MOD_SHIFT) & \ |
405 |
(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))) |
406 |
#define D_CHCR_MOD_NORMAL 0 |
407 |
#define D_CHCR_MOD_CHAIN 1 |
408 |
#define D_CHCR_MOD_INTERLEAVE 2 |
409 |
/* |
410 |
* DMA transfer direction (1 ... from Memory, 0 ... to Memory) |
411 |
* (VIF1, SIF2 only. i.e. `both'-direction channel requires this) |
412 |
*/ |
413 |
#define D_CHCR_DIR 0x00000001 |
414 |
|
415 |
/* |
416 |
* TRANSFER ADDRESS REGISTER (D-RAM address) |
417 |
* 16 byte alignment. In FROMSPR, TOSPR channel, D_MADR_SPR always 0 |
418 |
*/ |
419 |
#define D_MADR_SPR 0x80000000 |
420 |
|
421 |
/* |
422 |
* TAG ADDRESS REGISTER (next tag address) |
423 |
* 16 byte alignment. |
424 |
*/ |
425 |
#define D_TADR_SPR 0x80000000 |
426 |
|
427 |
/* |
428 |
* TAG ADDRESS STACK REGISTER (2 stage) |
429 |
* 16 byte alignment. |
430 |
*/ |
431 |
#define D_ASR_SPR 0x80000000 |
432 |
|
433 |
/* |
434 |
* SPR TRANSFER ADDRESS REGISTER (SPR address) |
435 |
* 16 byte alignment. FROMSPR, TOSPR only. |
436 |
*/ |
437 |
#define D_SADR_MASK 0x3fff |
438 |
#define D_SADR_SHIFT 0 |
439 |
#define D_SADR(x) \ |
440 |
((uint32_t)(x) & D_SADR_MASK) |
441 |
/* |
442 |
* TRANSFER SIZE REGISTER |
443 |
* min 16 byte to max 1 Mbyte. |
444 |
*/ |
445 |
#define D_QWC_MASK 0xffff |
446 |
#define D_QWC_SHIFT 0 |
447 |
#define D_QWC(x) (((x) >> D_QWC_SHIFT) & D_QWC_MASK) |
448 |
#define D_QWC_CLR(x) ((x) & ~(D_QWC_MASK << D_QWC_SHIFT)) |
449 |
#define D_QWC_SET(x, val) \ |
450 |
((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT)) |
451 |
|
452 |
/* |
453 |
* Source/Destination Chain Tag definition. |
454 |
* SC ... VIF0, VIF1, GIF, toIPU, SIF1, toSPR |
455 |
* DC ... SIF0, fromSPR |
456 |
*/ |
457 |
/* |
458 |
* DMA address |
459 |
* At least, 16byte align. |
460 |
* but 64byte align is recommended. because EE D-cash line size is 64byte. |
461 |
* To gain maximum DMA speed, use 128 byte align. |
462 |
*/ |
463 |
#define DMATAG_ADDR_MASK 0xffffffff |
464 |
#define DMATAG_ADDR_SHIFT 32 |
465 |
#define DMATAG_ADDR(x) \ |
466 |
((uint32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK)) |
467 |
#define DMATAG_ADDR_SET(x, val) \ |
468 |
((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT)) |
469 |
|
470 |
#define DMATAG_ADDR32_INVALID(x) ((x) & 0xf) /* 16byte alignment */ |
471 |
|
472 |
/* |
473 |
* DMA controller command |
474 |
*/ |
475 |
#define DMATAG_CMD_MASK 0xffffffff |
476 |
#define DMATAG_CMD_SHIFT 0 |
477 |
#define DMATAG_CMD(x) \ |
478 |
((uint32_t)((x) & DMATAG_CMD_MASK)) |
479 |
|
480 |
#define DMATAG_CMD_IRQ 0x80000000 |
481 |
|
482 |
#define DMATAG_CMD_ID_MASK 0x7 |
483 |
#define DMATAG_CMD_ID_SHIFT 28 |
484 |
#define DMATAG_CMD_ID(x) \ |
485 |
(((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK) |
486 |
#define DMATAG_CMD_ID_CLR(x) \ |
487 |
((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT)) |
488 |
#define DMATAG_CMD_ID_SET(x, val) \ |
489 |
((x) | (((val) << DMATAG_CMD_ID_SHIFT) & \ |
490 |
(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))) |
491 |
#define DMATAG_CMD_SCID_REFE 0 |
492 |
#define DMATAG_CMD_SCID_CNT 1 |
493 |
#define DMATAG_CMD_SCID_NEXT 2 |
494 |
#define DMATAG_CMD_SCID_REF 3 |
495 |
#define DMATAG_CMD_SCID_REFS 4 /* VIF1, GIF, SIF1 only */ |
496 |
#define DMATAG_CMD_SCID_CALL 5 /* VIF0, VIF1, GIF only */ |
497 |
#define DMATAG_CMD_SCID_RET 6 /* VIF0, VIF1, GIF only */ |
498 |
#define DMATAG_CMD_SCID_END 7 |
499 |
|
500 |
#define DMATAG_CMD_DCID_CNTS 0 /* SIF0, fromSPR only */ |
501 |
#define DMATAG_CMD_DCID_CNT 1 |
502 |
#define DMATAG_CMD_DCID_END 7 |
503 |
|
504 |
#define DMATAG_CMD_PCE_MASK 0x3 |
505 |
#define DMATAG_CMD_PCE_SHIFT 26 |
506 |
#define DMATAG_CMD_PCE(x) \ |
507 |
(((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK) |
508 |
#define DMATAG_CMD_PCE_CLR(x) \ |
509 |
((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT)) |
510 |
#define DMATAG_CMD_PCE_SET(x, val) \ |
511 |
((x) | (((val) << DMATAG_CMD_PCE_SHIFT) & \ |
512 |
(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))) |
513 |
#define DMATAG_CMD_PCE_NONE 0 |
514 |
#define DMATAG_CMD_PCE_DISABLE 2 |
515 |
#define DMATAG_CMD_PCE_ENABLE 3 |
516 |
|
517 |
#define DMATAG_CMD_QWC_MASK 0xffff |
518 |
#define DMATAG_CMD_QWC_SHIFT 0 |
519 |
#define DMATAG_CMD_QWC(x) \ |
520 |
(((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK) |
521 |
#define DMATAG_CMD_QWC_CLR(x) \ |
522 |
((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT)) |
523 |
#define DMATAG_CMD_QWC_SET(x, val) \ |
524 |
((x) | (((val) << DMATAG_CMD_QWC_SHIFT) & \ |
525 |
(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))) |
526 |
|
527 |
#endif /* PS2_DMACREG_H */ |