/[gxemul]/trunk/src/include/pica.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/pica.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (12 years ago) by dpavlin
File MIME type: text/plain
File size: 5895 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /* gxemul: $Id: pica.h,v 1.3 2005/03/05 12:34:03 debug Exp $ */
2 /* $NetBSD: pica.h,v 1.2 2001/06/13 15:11:38 soda Exp $ */
3 /* $OpenBSD: pica.h,v 1.4 1996/09/14 15:58:28 pefo Exp $ */
4
5 #ifndef _PICA_H_
6 #define _PICA_H_ 1
7
8 #define RELATIVE
9
10 /*
11 * Copyright (c) 1994, 1995, 1996 Per Fogelstrom
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed under OpenBSD by
24 * Per Fogelstrom.
25 * 4. The name of the author may not be used to endorse or promote products
26 * derived from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
29 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
30 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
32 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 */
41
42 /*
43 * PICA's Physical address space
44 */
45
46 #define PICA_PHYS_MIN 0x00000000 /* 256 Meg */
47 #define PICA_PHYS_MAX 0x0fffffff
48
49 /*
50 * Memory map
51 */
52
53 #define PICA_PHYS_MEMORY_START 0x00000000
54 #define PICA_PHYS_MEMORY_END 0x0fffffff /* 256 Meg in 8 slots */
55
56 #define PICA_MEMORY_SIZE_REG 0xe00fffe0 /* Memory size register */
57 #define PICA_CONFIG_REG 0xe00ffff0 /* Hardware config reg */
58
59 /*
60 * I/O map
61 */
62
63 #define R4030_P_LOCAL_IO_BASE 0x80000000 /* I/O Base address */
64 #define R4030_V_LOCAL_IO_BASE 0xe0000000
65 #define R4030_S_LOCAL_IO_BASE 0x00040000 /* Size */
66 #ifndef RELATIVE
67 #define R4030 R4030_V_LOCAL_IO_BASE
68 #else
69 #define R4030 0
70 #endif
71
72 #define R4030_SYS_CONFIG (R4030+0x0000) /* Global config register */
73 #define R4030_SYS_TL_BASE (R4030+0x0018) /* DMA transl. table base */
74 #define R4030_SYS_TL_LIMIT (R4030+0x0020) /* DMA transl. table limit */
75 #define R4030_SYS_TL_IVALID (R4030+0x0028) /* DMA transl. cache inval */
76 #define R4030_SYS_DMA0_REGS (R4030+0x0100) /* DMA ch0 base address */
77 #define R4030_SYS_DMA1_REGS (R4030+0x0120) /* DMA ch0 base address */
78 #define R4030_SYS_DMA2_REGS (R4030+0x0140) /* DMA ch0 base address */
79 #define R4030_SYS_DMA3_REGS (R4030+0x0160) /* DMA ch0 base address */
80 #define R4030_SYS_DMA_INT_SRC (R4030+0x0200) /* DMA int source status reg */
81 #define R4030_SYS_NVRAM_PROT (R4030+0x0220) /* NV ram protect register */
82 #define R4030_SYS_IT_VALUE (R4030+0x0228) /* Interval timer reload */
83 #define R4030_SYS_IT_STAT (R4030+0x0230) /* Interval timer count */
84 #define R4030_SYS_ISA_VECTOR (R4030+0x0238) /* ISA Interrupt vector */
85 #define R4030_SYS_EXT_IMASK (R4030+0x00e8) /* External int enable mask */
86
87 #ifndef RELATIVE
88 #define PVLB R4030_V_LOCAL_IO_BASE
89 #else
90 #define PVLB 0
91 #endif
92
93 #define PICA_SYS_SONIC (PVLB+0x1000) /* SONIC base address */
94 #define PICA_SYS_SCSI (PVLB+0x2000) /* SCSI base address */
95 #define PICA_SYS_FLOPPY (PVLB+0x3000) /* Floppy base address */
96 #define PICA_SYS_CLOCK (PVLB+0x4000) /* Clock base address */
97 #define PICA_SYS_KBD (PVLB+0x5000) /* Keybrd/mouse base address */
98 #define PICA_SYS_COM1 (PVLB+0x6000) /* Com port 1 */
99 #define PICA_SYS_COM2 (PVLB+0x7000) /* Com port 2 */
100 #define PICA_SYS_PAR1 (PVLB+0x8000) /* Parallel port 1 */
101 #define PICA_SYS_NVRAM (PVLB+0x9000) /* Unprotected NV-ram */
102 #define PICA_SYS_PNVRAM (PVLB+0xa000) /* Protected NV-ram */
103 #define PICA_SYS_NVPROM (PVLB+0xb000) /* Read only NV-ram */
104 #define PICA_SYS_SOUND (PVLB+0xc000) /* Sound port */
105
106 #define PICA_SYS_ISA_AS (PICA_V_ISA_IO+0x70)
107
108 #define PICA_P_DRAM_CONF 0x800e0000 /* Dram config registers */
109 #define PICA_V_DRAM_CONF 0xe00e0000
110 #define PICA_S_DRAM_CONF 0x00020000
111
112 #define PICA_P_INT_SOURCE 0xf0000000 /* Interrupt src registers */
113 #define PICA_V_INT_SOURCE R4030_V_LOCAL_IO_BASE+R4030_S_LOCAL_IO_BASE
114 #define PICA_S_INT_SOURCE 0x00001000
115 #define PVIS PICA_V_INT_SOURCE
116 #define PICA_SYS_LB_IS (PVIS+0x0000) /* Local bus int source */
117 #define PICA_SYS_LB_IE (PVIS+0x0002) /* Local bus int enables */
118
119 #define PICA_P_LOCAL_VIDEO_CTRL 0x60000000 /* Local video control */
120 #define PICA_V_LOCAL_VIDEO_CTRL 0xe0200000
121 #define PICA_S_LOCAL_VIDEO_CTRL 0x00200000
122
123 #define PICA_P_EXTND_VIDEO_CTRL 0x60200000 /* Extended video control */
124 #define PICA_V_EXTND_VIDEO_CTRL 0xe0400000
125 #define PICA_S_EXTND_VIDEO_CTRL 0x00200000
126
127 #define PICA_P_LOCAL_VIDEO 0x40000000 /* Local video memory */
128 #define PICA_V_LOCAL_VIDEO 0xe0800000
129 #define PICA_S_LOCAL_VIDEO 0x00800000
130
131 #define PICA_P_ISA_IO 0x90000000 /* ISA I/O control */
132 #define PICA_V_ISA_IO 0xe2000000
133 #define PICA_S_ISA_IO 0x01000000
134
135 #define PICA_P_ISA_MEM 0x91000000 /* ISA Memory control */
136 #define PICA_V_ISA_MEM 0xe3000000
137 #define PICA_S_ISA_MEM 0x01000000
138
139 /*
140 * Addresses used by various display drivers.
141 */
142 #define PICA_MONO_BASE (PICA_V_LOCAL_VIDEO_CTRL + 0x3B4)
143 #define PICA_MONO_BUF (PICA_V_LOCAL_VIDEO + 0xB0000)
144 #define PICA_CGA_BASE (PICA_V_LOCAL_VIDEO_CTRL + 0x3D4)
145 #define PICA_CGA_BUF (PICA_V_LOCAL_VIDEO + 0xB8000)
146
147 #endif /* _PICA_H_ */

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