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/* gxemul: $Id: pcireg.h,v 1.4 2005/03/05 12:34:03 debug Exp $ */ |
/* gxemul: $Id: pcireg.h,v 1.6 2005/11/17 13:53:43 debug Exp $ */ |
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/* $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $ */ |
/* $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $ */ |
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#ifndef _DEV_PCI_PCIREG_H_ |
#ifndef _DEV_PCI_PCIREG_H_ |
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(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) |
(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) |
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#define PCI_ID_CODE(vid,pid) \ |
#define PCI_ID_CODE(vid,pid) \ |
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((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ |
((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ |
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(((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ |
(((uint32_t)((pid) & PCI_PRODUCT_MASK)) << PCI_PRODUCT_SHIFT)) |
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/* |
/* |
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* Command and status register. |
* Command and status register. |
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#define PCI_COMMAND_STATUS_CODE(cmd,stat) \ |
#define PCI_COMMAND_STATUS_CODE(cmd,stat) \ |
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((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \ |
((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \ |
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(((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) \ |
(((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) |
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#define PCI_COMMAND_IO_ENABLE 0x00000001 |
#define PCI_COMMAND_IO_ENABLE 0x00000001 |
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#define PCI_COMMAND_MEM_ENABLE 0x00000002 |
#define PCI_COMMAND_MEM_ENABLE 0x00000002 |