/[gxemul]/trunk/src/include/opcodes_ppc.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/opcodes_ppc.h

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7776 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 #ifndef OPCODES_PPC_H
2 #define OPCODES_PPC_H
3
4 /*
5 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: opcodes_ppc.h,v 1.49 2006/03/05 16:51:55 debug Exp $
32 *
33 *
34 * PPC and POWER opcodes. These are gathered from various sources.
35 * Note: The define uses the PPC name, not the POWER name, when they differ.
36 */
37
38 #define PPC_HI6_MULLI 0x07
39 #define PPC_HI6_SUBFIC 0x08
40
41 #define PPC_HI6_CMPLI 0x0a
42 #define PPC_HI6_CMPI 0x0b
43 #define PPC_HI6_ADDIC 0x0c
44 #define PPC_HI6_ADDIC_DOT 0x0d
45 #define PPC_HI6_ADDI 0x0e
46 #define PPC_HI6_ADDIS 0x0f
47 #define PPC_HI6_BC 0x10
48 #define PPC_HI6_SC 0x11
49 #define PPC_HI6_B 0x12
50 #define PPC_HI6_19 0x13
51 #define PPC_19_MCRF 0
52 #define PPC_19_BCLR 16
53 #define PPC_19_RFID 18
54 #define PPC_19_CRNOR 33
55 #define PPC_19_RFI 50
56 #define PPC_19_RFSVC 82
57 #define PPC_19_CRANDC 129
58 #define PPC_19_ISYNC 150
59 #define PPC_19_CRXOR 193
60 #define PPC_19_CRNAND 225
61 #define PPC_19_CRAND 257
62 #define PPC_19_CREQV 289
63 #define PPC_19_CRORC 417
64 #define PPC_19_CROR 449
65 #define PPC_19_BCCTR 528
66 #define PPC_HI6_RLWIMI 0x14
67 #define PPC_HI6_RLWINM 0x15
68
69 #define PPC_HI6_RLWNM 0x17
70 #define PPC_HI6_ORI 0x18
71 #define PPC_HI6_ORIS 0x19
72 #define PPC_HI6_XORI 0x1a
73 #define PPC_HI6_XORIS 0x1b
74 #define PPC_HI6_ANDI_DOT 0x1c
75 #define PPC_HI6_ANDIS_DOT 0x1d
76 #define PPC_HI6_30 0x1e
77 #define PPC_30_RLDICL 0x0
78 #define PPC_30_RLDICR 0x1
79 #define PPC_30_RLDIMI 0x3
80 #define PPC_HI6_31 0x1f
81 #define PPC_31_CMP 0
82 #define PPC_31_TW 4
83 #define PPC_31_SUBFC 8
84 #define PPC_31_ADDC 10
85 #define PPC_31_MULHWU 11
86 #define PPC_31_MFCR 19
87 #define PPC_31_LWARX 20
88 #define PPC_31_LWZX 23
89 #define PPC_31_SLW 24
90 #define PPC_31_CNTLZW 26
91 #define PPC_31_SLD 27
92 #define PPC_31_AND 28
93 #define PPC_31_CMPL 32
94 #define PPC_31_SUBF 40
95 #define PPC_31_DCBST 54
96 #define PPC_31_LWZUX 55
97 #define PPC_31_ANDC 60
98 #define PPC_31_TD 68
99 #define PPC_31_MULHW 75
100 #define PPC_31_MFMSR 83
101 #define PPC_31_LDARX 84
102 #define PPC_31_DCBF 86
103 #define PPC_31_LBZX 87
104 #define PPC_31_LVX 103
105 #define PPC_31_NEG 104
106 #define PPC_31_CLF 118
107 #define PPC_31_LBZUX 119
108 #define PPC_31_NOR 124
109 #define PPC_31_SUBFE 136
110 #define PPC_31_ADDE 138
111 #define PPC_31_MTCRF 144
112 #define PPC_31_MTMSR 146
113 #define PPC_31_STDX 149
114 #define PPC_31_STWCX_DOT 150
115 #define PPC_31_STWX 151
116 #define PPC_31_WRTEEI 163
117 #define PPC_31_MTMSRD 178
118 #define PPC_31_STDUX 181
119 #define PPC_31_STWUX 183
120 #define PPC_31_SUBFZE 200
121 #define PPC_31_ADDZE 202
122 #define PPC_31_MTSR 210
123 #define PPC_31_STDCX_DOT 214
124 #define PPC_31_STBX 215
125 #define PPC_31_STVX 231
126 #define PPC_31_SUBFME 232
127 #define PPC_31_ADDME 234
128 #define PPC_31_MULLW 235
129 #define PPC_31_MTSRIN 242
130 #define PPC_31_DCBTST 246
131 #define PPC_31_STBUX 247
132 #define PPC_31_ADD 266
133 #define PPC_31_DCBT 278
134 #define PPC_31_LHZX 279
135 #define PPC_31_EQV 284
136 #define PPC_31_TLBIE 306
137 #define PPC_31_LHZUX 311
138 #define PPC_31_XOR 316
139 #define PPC_31_MFSPR 339
140 #define PPC_31_LHAX 343
141 #define PPC_31_LVXL 359
142 #define PPC_31_TLBIA 370
143 #define PPC_31_MFTB 371
144 #define PPC_31_LHAUX 375
145 #define PPC_31_STHX 407
146 #define PPC_31_ORC 412
147 #define PPC_31_SLBIE 434
148 #define PPC_31_STHUX 439
149 #define PPC_31_OR 444
150 #define PPC_31_DCCCI 454
151 #define PPC_31_DIVWU 459
152 #define PPC_31_MTSPR 467
153 #define PPC_31_DCBI 470
154 #define PPC_31_NAND 476
155 #define PPC_31_STVXL 487
156 #define PPC_31_DIVW 491
157 #define PPC_31_SLBIA 498
158 #define PPC_31_CLI 502
159 #define PPC_31_SUBFCO 520
160 #define PPC_31_ADDCO 522
161 #define PPC_31_LWBRX 534
162 #define PPC_31_LFSX 535
163 #define PPC_31_SRW 536
164 #define PPC_31_SUBFO 552
165 #define PPC_31_TLBSYNC 566
166 #define PPC_31_MFSR 595
167 #define PPC_31_LSWI 597
168 #define PPC_31_SYNC 598
169 #define PPC_31_LFDX 599
170 #define PPC_31_NEGO 616
171 #define PPC_31_DCLST 630
172 #define PPC_31_SUBFEO 648
173 #define PPC_31_ADDEO 650
174 #define PPC_31_MFSRIN 659
175 #define PPC_31_STWBRX 662
176 #define PPC_31_STFSX 663
177 #define PPC_31_SUBFZEO 712
178 #define PPC_31_ADDZEO 714
179 #define PPC_31_STSWI 725
180 #define PPC_31_STFDX 727
181 #define PPC_31_SUBFMEO 744
182 #define PPC_31_ADDMEO 746
183 #define PPC_31_MULLWO 747
184 #define PPC_31_ADDO 778
185 #define PPC_31_LHBRX 790
186 #define PPC_31_SRAW 792
187 #define PPC_31_DSSALL 822
188 #define PPC_31_SRAWI 824
189 #define PPC_31_EIEIO 854
190 #define PPC_31_TLBSX_DOT 914
191 #define PPC_31_STHBRX 918
192 #define PPC_31_EXTSH 922
193 #define PPC_31_EXTSB 954
194 #define PPC_31_ICCCI 966
195 #define PPC_31_DIVWUO 971
196 #define PPC_31_TLBLD 978
197 #define PPC_31_ICBI 982
198 #define PPC_31_EXTSW 986
199 #define PPC_31_DIVWO 1003
200 #define PPC_31_TLBLI 1010
201 #define PPC_31_DCBZ 1014
202 #define PPC_HI6_LWZ 0x20
203 #define PPC_HI6_LWZU 0x21
204 #define PPC_HI6_LBZ 0x22
205 #define PPC_HI6_LBZU 0x23
206 #define PPC_HI6_STW 0x24
207 #define PPC_HI6_STWU 0x25
208 #define PPC_HI6_STB 0x26
209 #define PPC_HI6_STBU 0x27
210 #define PPC_HI6_LHZ 0x28
211 #define PPC_HI6_LHZU 0x29
212 #define PPC_HI6_LHA 0x2a
213 #define PPC_HI6_LHAU 0x2b
214 #define PPC_HI6_STH 0x2c
215 #define PPC_HI6_STHU 0x2d
216 #define PPC_HI6_LMW 0x2e
217 #define PPC_HI6_STMW 0x2f
218 #define PPC_HI6_LFS 0x30
219
220 #define PPC_HI6_LFD 0x32
221
222 #define PPC_HI6_STFS 0x34
223
224 #define PPC_HI6_STFD 0x36
225
226 #define PPC_HI6_LD 0x3a
227 #define PPC_HI6_59 0x3b
228 #define PPC_59_FDIVS 18
229 #define PPC_59_FSUBS 20
230 #define PPC_59_FADDS 21
231 #define PPC_59_FMULS 25
232 #define PPC_59_FMADDS 29
233
234 #define PPC_HI6_STD 0x3e
235 #define PPC_HI6_63 0x3f
236 #define PPC_63_FCMPU 0
237 #define PPC_63_FRSP 12
238 #define PPC_63_FCTIWZ 15
239 #define PPC_63_FDIV 18
240 #define PPC_63_FSUB 20
241 #define PPC_63_FADD 21
242 #define PPC_63_FMUL 25
243 #define PPC_63_FMSUB 28
244 #define PPC_63_FMADD 29
245 #define PPC_63_FNEG 40
246 #define PPC_63_FMR 72
247 #define PPC_63_FNABS 136
248 #define PPC_63_FABS 264
249 #define PPC_63_MFFS 583
250 #define PPC_63_MTFSF 711
251
252 #endif /* OPCODES_PPC_H */

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