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++ trunk/HISTORY (local) $Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $ 20061029 Changing usleep(1) calls in the debugger to usleep(10000) 20061107 Adding a new disk image option (-d o...) which sets the ISO9660 filesystem base offset; also making some other hacks to allow NetBSD/dreamcast and homebrew demos/games to boot directly from a filesystem image. Moving Dreamcast-specific stuff in the documentation to its own page (dreamcast.html). Adding a border to the Dreamcast PVR framebuffer. 20061108 Adding a -T command line option (again?), for halting the emulator on unimplemented memory accesses. 20061109 Continuing on various SH4 and Dreamcast related things. The emulator should now halt on more unimplemented device accesses, instead of just printing a warning, forcing me to actually implement missing stuff :) 20061111 Continuing on SH4 and Dreamcast stuff. Adding a bogus Landisk (SH4) machine mode. 20061112 Implementing some parts of the Dreamcast GDROM device. With some ugly hacks, NetBSD can (barely) mount an ISO image. 20061113 NetBSD/dreamcast now starts booting from the Live CD image, but crashes randomly quite early on in the boot process. 20061122 Beginning on a skeleton interrupt.h and interrupt.c for the new interrupt subsystem. 20061124 Continuing on the new interrupt system; taking the first steps to attempt to connect CPUs (SuperH and MIPS) and devices (dev_cons and SH4 timer interrupts) to it. Many things will probably break from now on. 20061125 Converting dev_ns16550, dev_8253 to the new interrupt system. Attempting to begin to convert the ISA bus. 20061130 Incorporating a patch from Brian Foley for the configure script, which checks for X11 libs in /usr/X11R6/lib64 (which is used on some Linux systems). 20061227 Adding a note in the man page about booting from Dreamcast CDROM images (i.e. that no external kernel is needed). 20061229 Continuing on the interrupt system rewrite: beginning to convert more devices, adding abort() calls for legacy interrupt system calls so that everything now _has_ to be rewritten! Almost all machine modes are now completely broken. 20061230 More progress on removing old interrupt code, mostly related to the ISA bus + devices, the LCA bus (on AlphaBook1), and the Footbridge bus (for CATS). And some minor PCI stuff. Connecting the ARM cpu to the new interrupt system. The CATS, NetWinder, and QEMU_MIPS machine modes now work with the new interrupt system :) 20061231 Connecting PowerPC CPUs to the new interrupt system. Making PReP machines (IBM 6050) work again. Beginning to convert the GT PCI controller (for e.g. Malta and Cobalt emulation). Some things work, but not everything. Updating Copyright notices for 2007. 20070101 Converting dev_kn02 from legacy style to devinit; the 3max machine mode now works with the new interrupt system :-] 20070105 Beginning to convert the SGI O2 machine to the new interrupt system; finally converting O2 (IP32) devices to devinit, etc. 20070106 Continuing on the interrupt system redesign/rewrite; KN01 (PMAX), KN230, and Dreamcast ASIC interrupts should work again, moving out stuff from machine.h and devices.h into the corresponding devices, beginning the rewrite of i80321 interrupts, etc. 20070107 Beginning on the rewrite of Eagle interrupt stuff (PReP, etc). 20070117 Beginning the rewrite of Algor (V3) interrupts (finally changing dev_v3 into devinit style). 20070118 Removing the "bus" registry concept from machine.h, because it was practically meaningless. Continuing on the rewrite of Algor V3 ISA interrupts. 20070121 More work on Algor interrupts; they are now working again, well enough to run NetBSD/algor. :-) 20070122 Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips can be installed using the new interrupt system :-) 20070123 Making the testmips mode work with the new interrupt system. 20070127 Beginning to convert DEC5800 devices to devinit, and to the new interrupt system. Converting Playstation 2 devices to devinit, and converting the interrupt system. Also fixing a severe bug: the interrupt mask register on Playstation 2 is bitwise _toggled_ on writes. 20070128 Removing the dummy NetGear machine mode and the 8250 device (which was only used by the NetGear machine). Beginning to convert the MacPPC GC (Grand Central) interrupt controller to the new interrupt system. Converting Jazz interrupts (PICA61 etc.) to the new interrupt system. NetBSD/arc can be installed again :-) Fixing the JAZZ timer (hardcoding it at 100 Hz, works with NetBSD and it is better than a completely dummy timer as it was before). Converting dev_mp to the new interrupt system, although I haven't had time to actually test it yet. Completely removing src/machines/interrupts.c, cpu_interrupt and cpu_interrupt_ack in src/cpu.c, and src/include/machine_interrupts.h! Adding fatal error messages + abort() in the few places that are left to fix. Converting dev_z8530 to the new interrupt system. FINALLY removing the md_int struct completely from the machine struct. SH4 fixes (adding a PADDR invalidation in the ITLB replacement code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs all the way to the login prompt, and can be interacted with :-) Converting the CPC700 controller (PCI and interrupt controller for PM/PPC) to the new interrupt system. 20070129 Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/ sgimips' and OpenBSD/sgi's ramdisk kernels can now be interacted with again. 20070130 Moving out the MIPS multi_lw and _sw instruction combinations so that they are auto-generated at compile time instead. 20070131 Adding detection of amd64/x86_64 hosts in the configure script, for doing initial experiments (again :-) with native code generation. Adding a -k command line option to set the size of the dyntrans cache, and a -B command line option to disable native code generation, even if GXemul was compiled with support for native code generation for the specific host CPU architecture. 20070201 Experimenting with a skeleton for native code generation. Changing the default behaviour, so that native code generation is now disabled by default, and has to be enabled by using -b on the command line. 20070202 Continuing the native code generation experiments. Making PCI interrupts work for Footbridge again. 20070203 More native code generation experiments. Removing most of the native code generation experimental code, it does not make sense to include any quick hacks like this. Minor cleanup/removal of some more legacy MIPS interrupt code. 20070204 Making i80321 interrupts work again (for NetBSD/evbarm etc.), and fixing the timer at 100 Hz. 20070206 Experimenting with removing the wdc interrupt slowness hack. 20070207 Lowering the number of dyntrans TLB entries for MIPS from 192 to 128, resulting in a minor speed improvement. Minor optimization to the code invalidation routine in cpu_dyntrans.c. 20070208 Increasing (experimentally) the nr of dyntrans instructions per loop from 60 to 120. 20070210 Commenting out (experimentally) the dyntrans_device_danger detection in memory_rw.c. Changing the testmips and baremips machines to use a revision 2 MIPS64 CPU by default, instead of revision 1. Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC files, the PC bios emulation, and the Olivetti M700 (ARC) and db64360 emulation modes. 20070211 Adding an "mp" demo to the demos directory, which tests the SMP functionality of the testmips machine. Fixing PReP interrupts some more. NetBSD/prep now boots again. 20070216 Adding a "nop workaround" for booting Mach/PMAX to the documentation; thanks to Artur Bujdoso for the values. Converting more of the MacPPC interrupt stuff to the new system. Beginning to convert BeBox interrupts to the new system. PPC603e should NOT have the PPC_NO_DEC flag! Removing it. Correcting BeBox clock speed (it was set to 100 in the NetBSD bootinfo block, but should be 33000000/4), allowing NetBSD to start without using the (incorrect) PPC_NO_DEC hack. 20070217 Implementing (slow) AltiVec vector loads and stores, allowing NetBSD/macppc to finally boot using the GENERIC kernel :-) Updating the documentation with install instructions for NetBSD/macppc. 20070218-19 Regression testing for the release. ============== RELEASE 0.4.4 ==============
1 | dpavlin | 4 | #ifndef OPCODES_PPC_H |
2 | #define OPCODES_PPC_H | ||
3 | |||
4 | /* | ||
5 | dpavlin | 34 | * Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
6 | dpavlin | 4 | * |
7 | * Redistribution and use in source and binary forms, with or without | ||
8 | * modification, are permitted provided that the following conditions are met: | ||
9 | * | ||
10 | * 1. Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * 2. Redistributions in binary form must reproduce the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer in the | ||
14 | * documentation and/or other materials provided with the distribution. | ||
15 | * 3. The name of the author may not be used to endorse or promote products | ||
16 | * derived from this software without specific prior written permission. | ||
17 | * | ||
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | ||
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | ||
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
28 | * SUCH DAMAGE. | ||
29 | * | ||
30 | * | ||
31 | dpavlin | 34 | * $Id: opcodes_ppc.h,v 1.50 2006/12/30 13:31:01 debug Exp $ |
32 | dpavlin | 4 | * |
33 | * | ||
34 | dpavlin | 12 | * PPC and POWER opcodes. These are gathered from various sources. |
35 | dpavlin | 4 | * Note: The define uses the PPC name, not the POWER name, when they differ. |
36 | */ | ||
37 | |||
38 | #define PPC_HI6_MULLI 0x07 | ||
39 | #define PPC_HI6_SUBFIC 0x08 | ||
40 | |||
41 | #define PPC_HI6_CMPLI 0x0a | ||
42 | #define PPC_HI6_CMPI 0x0b | ||
43 | #define PPC_HI6_ADDIC 0x0c | ||
44 | #define PPC_HI6_ADDIC_DOT 0x0d | ||
45 | #define PPC_HI6_ADDI 0x0e | ||
46 | #define PPC_HI6_ADDIS 0x0f | ||
47 | #define PPC_HI6_BC 0x10 | ||
48 | #define PPC_HI6_SC 0x11 | ||
49 | #define PPC_HI6_B 0x12 | ||
50 | #define PPC_HI6_19 0x13 | ||
51 | #define PPC_19_MCRF 0 | ||
52 | #define PPC_19_BCLR 16 | ||
53 | dpavlin | 14 | #define PPC_19_RFID 18 |
54 | dpavlin | 4 | #define PPC_19_CRNOR 33 |
55 | dpavlin | 14 | #define PPC_19_RFI 50 |
56 | #define PPC_19_RFSVC 82 | ||
57 | dpavlin | 4 | #define PPC_19_CRANDC 129 |
58 | #define PPC_19_ISYNC 150 | ||
59 | #define PPC_19_CRXOR 193 | ||
60 | #define PPC_19_CRNAND 225 | ||
61 | #define PPC_19_CRAND 257 | ||
62 | #define PPC_19_CREQV 289 | ||
63 | #define PPC_19_CRORC 417 | ||
64 | #define PPC_19_CROR 449 | ||
65 | #define PPC_19_BCCTR 528 | ||
66 | #define PPC_HI6_RLWIMI 0x14 | ||
67 | #define PPC_HI6_RLWINM 0x15 | ||
68 | |||
69 | dpavlin | 20 | #define PPC_HI6_RLWNM 0x17 |
70 | dpavlin | 4 | #define PPC_HI6_ORI 0x18 |
71 | #define PPC_HI6_ORIS 0x19 | ||
72 | #define PPC_HI6_XORI 0x1a | ||
73 | #define PPC_HI6_XORIS 0x1b | ||
74 | #define PPC_HI6_ANDI_DOT 0x1c | ||
75 | #define PPC_HI6_ANDIS_DOT 0x1d | ||
76 | #define PPC_HI6_30 0x1e | ||
77 | #define PPC_30_RLDICL 0x0 | ||
78 | #define PPC_30_RLDICR 0x1 | ||
79 | dpavlin | 24 | #define PPC_30_RLDIMI 0x3 |
80 | dpavlin | 4 | #define PPC_HI6_31 0x1f |
81 | #define PPC_31_CMP 0 | ||
82 | dpavlin | 14 | #define PPC_31_TW 4 |
83 | dpavlin | 4 | #define PPC_31_SUBFC 8 |
84 | #define PPC_31_ADDC 10 | ||
85 | #define PPC_31_MULHWU 11 | ||
86 | #define PPC_31_MFCR 19 | ||
87 | dpavlin | 14 | #define PPC_31_LWARX 20 |
88 | dpavlin | 4 | #define PPC_31_LWZX 23 |
89 | #define PPC_31_SLW 24 | ||
90 | #define PPC_31_CNTLZW 26 | ||
91 | dpavlin | 24 | #define PPC_31_SLD 27 |
92 | dpavlin | 4 | #define PPC_31_AND 28 |
93 | #define PPC_31_CMPL 32 | ||
94 | #define PPC_31_SUBF 40 | ||
95 | #define PPC_31_DCBST 54 | ||
96 | #define PPC_31_LWZUX 55 | ||
97 | #define PPC_31_ANDC 60 | ||
98 | dpavlin | 14 | #define PPC_31_TD 68 |
99 | dpavlin | 4 | #define PPC_31_MULHW 75 |
100 | #define PPC_31_MFMSR 83 | ||
101 | dpavlin | 14 | #define PPC_31_LDARX 84 |
102 | dpavlin | 12 | #define PPC_31_DCBF 86 |
103 | dpavlin | 4 | #define PPC_31_LBZX 87 |
104 | dpavlin | 22 | #define PPC_31_LVX 103 |
105 | dpavlin | 4 | #define PPC_31_NEG 104 |
106 | dpavlin | 12 | #define PPC_31_CLF 118 |
107 | dpavlin | 4 | #define PPC_31_LBZUX 119 |
108 | #define PPC_31_NOR 124 | ||
109 | #define PPC_31_SUBFE 136 | ||
110 | #define PPC_31_ADDE 138 | ||
111 | #define PPC_31_MTCRF 144 | ||
112 | #define PPC_31_MTMSR 146 | ||
113 | dpavlin | 12 | #define PPC_31_STDX 149 |
114 | dpavlin | 14 | #define PPC_31_STWCX_DOT 150 |
115 | dpavlin | 4 | #define PPC_31_STWX 151 |
116 | dpavlin | 22 | #define PPC_31_WRTEEI 163 |
117 | dpavlin | 24 | #define PPC_31_MTMSRD 178 |
118 | dpavlin | 12 | #define PPC_31_STDUX 181 |
119 | dpavlin | 4 | #define PPC_31_STWUX 183 |
120 | #define PPC_31_SUBFZE 200 | ||
121 | #define PPC_31_ADDZE 202 | ||
122 | #define PPC_31_MTSR 210 | ||
123 | dpavlin | 14 | #define PPC_31_STDCX_DOT 214 |
124 | dpavlin | 4 | #define PPC_31_STBX 215 |
125 | dpavlin | 22 | #define PPC_31_STVX 231 |
126 | dpavlin | 20 | #define PPC_31_SUBFME 232 |
127 | dpavlin | 14 | #define PPC_31_ADDME 234 |
128 | dpavlin | 4 | #define PPC_31_MULLW 235 |
129 | #define PPC_31_MTSRIN 242 | ||
130 | dpavlin | 12 | #define PPC_31_DCBTST 246 |
131 | dpavlin | 4 | #define PPC_31_STBUX 247 |
132 | #define PPC_31_ADD 266 | ||
133 | dpavlin | 12 | #define PPC_31_DCBT 278 |
134 | dpavlin | 4 | #define PPC_31_LHZX 279 |
135 | dpavlin | 24 | #define PPC_31_EQV 284 |
136 | dpavlin | 4 | #define PPC_31_TLBIE 306 |
137 | #define PPC_31_LHZUX 311 | ||
138 | #define PPC_31_XOR 316 | ||
139 | #define PPC_31_MFSPR 339 | ||
140 | dpavlin | 20 | #define PPC_31_LHAX 343 |
141 | dpavlin | 24 | #define PPC_31_LVXL 359 |
142 | dpavlin | 20 | #define PPC_31_TLBIA 370 |
143 | dpavlin | 4 | #define PPC_31_MFTB 371 |
144 | dpavlin | 20 | #define PPC_31_LHAUX 375 |
145 | dpavlin | 4 | #define PPC_31_STHX 407 |
146 | #define PPC_31_ORC 412 | ||
147 | dpavlin | 20 | #define PPC_31_SLBIE 434 |
148 | dpavlin | 4 | #define PPC_31_STHUX 439 |
149 | #define PPC_31_OR 444 | ||
150 | #define PPC_31_DCCCI 454 | ||
151 | #define PPC_31_DIVWU 459 | ||
152 | #define PPC_31_MTSPR 467 | ||
153 | dpavlin | 12 | #define PPC_31_DCBI 470 |
154 | dpavlin | 4 | #define PPC_31_NAND 476 |
155 | dpavlin | 22 | #define PPC_31_STVXL 487 |
156 | dpavlin | 4 | #define PPC_31_DIVW 491 |
157 | dpavlin | 20 | #define PPC_31_SLBIA 498 |
158 | dpavlin | 12 | #define PPC_31_CLI 502 |
159 | dpavlin | 4 | #define PPC_31_SUBFCO 520 |
160 | #define PPC_31_ADDCO 522 | ||
161 | dpavlin | 12 | #define PPC_31_LWBRX 534 |
162 | dpavlin | 20 | #define PPC_31_LFSX 535 |
163 | dpavlin | 4 | #define PPC_31_SRW 536 |
164 | #define PPC_31_SUBFO 552 | ||
165 | #define PPC_31_TLBSYNC 566 | ||
166 | dpavlin | 20 | #define PPC_31_MFSR 595 |
167 | dpavlin | 4 | #define PPC_31_LSWI 597 |
168 | #define PPC_31_SYNC 598 | ||
169 | dpavlin | 20 | #define PPC_31_LFDX 599 |
170 | dpavlin | 4 | #define PPC_31_NEGO 616 |
171 | dpavlin | 12 | #define PPC_31_DCLST 630 |
172 | dpavlin | 4 | #define PPC_31_SUBFEO 648 |
173 | #define PPC_31_ADDEO 650 | ||
174 | #define PPC_31_MFSRIN 659 | ||
175 | dpavlin | 12 | #define PPC_31_STWBRX 662 |
176 | dpavlin | 20 | #define PPC_31_STFSX 663 |
177 | dpavlin | 4 | #define PPC_31_SUBFZEO 712 |
178 | #define PPC_31_ADDZEO 714 | ||
179 | #define PPC_31_STSWI 725 | ||
180 | dpavlin | 20 | #define PPC_31_STFDX 727 |
181 | #define PPC_31_SUBFMEO 744 | ||
182 | dpavlin | 14 | #define PPC_31_ADDMEO 746 |
183 | dpavlin | 4 | #define PPC_31_MULLWO 747 |
184 | #define PPC_31_ADDO 778 | ||
185 | dpavlin | 12 | #define PPC_31_LHBRX 790 |
186 | dpavlin | 4 | #define PPC_31_SRAW 792 |
187 | dpavlin | 24 | #define PPC_31_DSSALL 822 |
188 | dpavlin | 4 | #define PPC_31_SRAWI 824 |
189 | #define PPC_31_EIEIO 854 | ||
190 | dpavlin | 22 | #define PPC_31_TLBSX_DOT 914 |
191 | dpavlin | 12 | #define PPC_31_STHBRX 918 |
192 | dpavlin | 4 | #define PPC_31_EXTSH 922 |
193 | #define PPC_31_EXTSB 954 | ||
194 | #define PPC_31_ICCCI 966 | ||
195 | #define PPC_31_DIVWUO 971 | ||
196 | dpavlin | 20 | #define PPC_31_TLBLD 978 |
197 | dpavlin | 4 | #define PPC_31_ICBI 982 |
198 | #define PPC_31_EXTSW 986 | ||
199 | #define PPC_31_DIVWO 1003 | ||
200 | dpavlin | 20 | #define PPC_31_TLBLI 1010 |
201 | dpavlin | 12 | #define PPC_31_DCBZ 1014 |
202 | dpavlin | 4 | #define PPC_HI6_LWZ 0x20 |
203 | #define PPC_HI6_LWZU 0x21 | ||
204 | #define PPC_HI6_LBZ 0x22 | ||
205 | #define PPC_HI6_LBZU 0x23 | ||
206 | #define PPC_HI6_STW 0x24 | ||
207 | #define PPC_HI6_STWU 0x25 | ||
208 | #define PPC_HI6_STB 0x26 | ||
209 | #define PPC_HI6_STBU 0x27 | ||
210 | #define PPC_HI6_LHZ 0x28 | ||
211 | #define PPC_HI6_LHZU 0x29 | ||
212 | #define PPC_HI6_LHA 0x2a | ||
213 | #define PPC_HI6_LHAU 0x2b | ||
214 | #define PPC_HI6_STH 0x2c | ||
215 | #define PPC_HI6_STHU 0x2d | ||
216 | #define PPC_HI6_LMW 0x2e | ||
217 | #define PPC_HI6_STMW 0x2f | ||
218 | dpavlin | 20 | #define PPC_HI6_LFS 0x30 |
219 | dpavlin | 4 | |
220 | #define PPC_HI6_LFD 0x32 | ||
221 | |||
222 | dpavlin | 20 | #define PPC_HI6_STFS 0x34 |
223 | |||
224 | dpavlin | 4 | #define PPC_HI6_STFD 0x36 |
225 | |||
226 | dpavlin | 20 | #define PPC_HI6_LD 0x3a |
227 | #define PPC_HI6_59 0x3b | ||
228 | #define PPC_59_FDIVS 18 | ||
229 | #define PPC_59_FSUBS 20 | ||
230 | #define PPC_59_FADDS 21 | ||
231 | #define PPC_59_FMULS 25 | ||
232 | #define PPC_59_FMADDS 29 | ||
233 | |||
234 | #define PPC_HI6_STD 0x3e | ||
235 | dpavlin | 14 | #define PPC_HI6_63 0x3f |
236 | dpavlin | 20 | #define PPC_63_FCMPU 0 |
237 | #define PPC_63_FRSP 12 | ||
238 | #define PPC_63_FCTIWZ 15 | ||
239 | #define PPC_63_FDIV 18 | ||
240 | #define PPC_63_FSUB 20 | ||
241 | #define PPC_63_FADD 21 | ||
242 | #define PPC_63_FMUL 25 | ||
243 | #define PPC_63_FMSUB 28 | ||
244 | #define PPC_63_FMADD 29 | ||
245 | #define PPC_63_FNEG 40 | ||
246 | dpavlin | 14 | #define PPC_63_FMR 72 |
247 | dpavlin | 20 | #define PPC_63_FNABS 136 |
248 | #define PPC_63_FABS 264 | ||
249 | #define PPC_63_MFFS 583 | ||
250 | #define PPC_63_MTFSF 711 | ||
251 | dpavlin | 14 | |
252 | dpavlin | 4 | #endif /* OPCODES_PPC_H */ |
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