/[gxemul]/trunk/src/include/opcodes_mips.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/include/opcodes_mips.h

Parent Directory Parent Directory | Revision Log Revision Log

Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 24984 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============
1 #ifndef OPCODES_MIPS_H
2 #define OPCODES_MIPS_H
3
4 /*
5 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: opcodes_mips.h,v 1.14 2006/08/11 17:43:30 debug Exp $
32 *
33 * MIPS opcodes, gathered from various sources.
34 *
35 * There are quite a number of different MIPS instruction sets, some are
36 * subsets/supersets of others, but not all of them.
37 *
38 * MIPS ISA I, II, III, IV: Backward-compatible ISAs used in R2000/R3000
39 * (ISA I), R6000 (ISA II), R4000 (ISA III),
40 * and R5000/R1x000 (ISA IV).
41 *
42 * MIPS ISA V: Never implemented in hardware?
43 *
44 * MIPS32 and MIPS64: The "modern" version of the ISA. These exist
45 * in a revision 1, and a revision 2 (the latest
46 * at the time of writing this).
47 *
48 * MIPS16: A special encoding form for MIPS32/64 which
49 * uses 16-bit instruction words instead of
50 * 32-bit.
51 *
52 * MDMX: MIPS Digital Media Extension.
53 *
54 * MIPS 3D: 3D instructions.
55 *
56 * MIPS MT: Multi-Threaded stuff.
57 */
58
59
60 /* Opcodes: */
61
62 #define HI6_NAMES { \
63 "special", "regimm", "j", "jal", "beq", "bne", "blez", "bgtz", /* 0x00 - 0x07 */ \
64 "addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui", /* 0x08 - 0x0f */ \
65 "cop0", "cop1", "cop2", "cop3", "beql", "bnel", "blezl", "bgtzl", /* 0x10 - 0x17 */ \
66 "daddi", "daddiu", "ldl", "ldr", "special2", "hi6_1d","lq" /*mdmx*/, "sq" /*special3*/, /* 0x18 - 0x1f */\
67 "lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "lwu", /* 0x20 - 0x27 */ \
68 "sb", "sh", "swl", "sw", "sdl", "sdr", "swr", "cache", /* 0x28 - 0x2f */ \
69 "ll", "lwc1", "lwc2", "lwc3", "lld", "ldc1", "ldc2", "ld", /* 0x30 - 0x37 */ \
70 "sc", "swc1", "swc2", "swc3", "scd", "sdc1", "sdc2", "sd" /* 0x38 - 0x3f */ }
71
72 #define REGIMM_NAMES { \
73 "bltz", "bgez", "bltzl", "bgezl", "regimm_04", "regimm_05", "regimm_06", "regimm_07", /* 0x00 - 0x07 */ \
74 "tgei", "tgeiu", "tlti", "tltiu", "teqi", "regimm_0d", "tnei", "regimm_0f", /* 0x08 - 0x0f */ \
75 "bltzal", "bgezal", "bltzall", "bgezall", "regimm_14", "regimm_15", "regimm_16", "regimm_17", /* 0x10 - 0x17 */ \
76 "mtsab", "mtsah", "regimm_1a", "regimm_1b", "regimm_1c", "regimm_1d", "regimm_1e", "synci" /* 0x18 - 0x1f */ }
77
78 #define SPECIAL_NAMES { \
79 "sll", "special_01", "srl", "sra", "sllv", "special_05", "srlv", "srav", /* 0x00 - 0x07 */ \
80 "jr", "jalr", "movz", "movn", "syscall","break", "special_0e", "sync", /* 0x08 - 0x0f */ \
81 "mfhi", "mthi", "mflo", "mtlo", "dsllv", "special_15", "dsrlv", "dsrav", /* 0x10 - 0x17 */ \
82 "mult", "multu", "div", "divu", "dmult", "dmultu", "ddiv", "ddivu", /* 0x18 - 0x1f */ \
83 "add", "addu", "sub", "subu", "and", "or", "xor", "nor", /* 0x20 - 0x27 */ \
84 "special_28","special_29","slt", "sltu", "dadd", "daddu", "dsub", "dsubu", /* 0x28 - 0x2f */ \
85 "tge", "tgeu", "tlt", "tltu", "teq", "special_35", "tne", "special_37",/* 0x30 - 0x37 */ \
86 "dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32" /* 0x38 - 0x3f */ }
87
88 #define SPECIAL2_NAMES { \
89 "madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \
90 "special2_08", "special2_09", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \
91 "special2_10", "special2_11", "special2_12", "special2_13", "special2_14", "special2_15", "special2_16", "special2_17", /* 0x10 - 0x17 */ \
92 "special2_18", "special2_19", "special2_1a", "special2_1b", "special2_1c", "special2_1d", "special2_1e", "special2_1f", /* 0x18 - 0x1f */ \
93 "clz", "clo", "special2_22", "special2_23", "dclz", "dclo", "special2_26", "special2_27", /* 0x20 - 0x27 */ \
94 "special2_28", "special2_29", "special2_2a", "special2_2b", "special2_2c", "special2_2d", "special2_2e", "special2_2f", /* 0x28 - 0x2f */ \
95 "special2_30", "special2_31", "special2_32", "special2_33", "special2_34", "special2_35", "special2_36", "special2_37", /* 0x30 - 0x37 */ \
96 "special2_38", "special2_39", "special2_3a", "special2_3b", "special2_3c", "special2_3d", "special2_3e", "sdbbp" /* 0x38 - 0x3f */ }
97
98 /* MMI (on R5900, TX79/C790) occupies the same space as SPECIAL2 */
99 #define MMI_NAMES { \
100 "madd", "maddu", "mmi_02", "mmi_03", "plzcw", "mmi_05", "mmi_06", "mmi_07", /* 0x00 - 0x07 */ \
101 "mmi0", "mmi2", "mmi_0a", "mmi_0b", "mmi_0c", "mmi_0d", "mmi_0e", "mmi_0f", /* 0x08 - 0x0f */ \
102 "mfhi1", "mthi1", "mflo1", "mtlo1", "mmi_14", "mmi_15", "mmi_16", "mmi_17", /* 0x10 - 0x17 */ \
103 "mult1", "multu1", "div1", "divu1", "mmi_1c", "mmi_1d", "mmi_1e", "mmi_1f", /* 0x18 - 0x1f */ \
104 "madd1", "maddu1", "mmi_22", "mmi_23", "mmi_24", "mmi_25", "mmi_26", "mmi_27", /* 0x20 - 0x27 */ \
105 "mmi1", "mmi3", "mmi_2a", "mmi_2b", "mmi_2c", "mmi_2d", "mmi_2e", "mmi_2f", /* 0x28 - 0x2f */ \
106 "pmfhl", "pmthl", "mmi_32", "mmi_33", "psllh", "mmi_35", "psrlh", "psrah", /* 0x30 - 0x37 */ \
107 "mmi_38", "mmi_39", "mmi_3a", "mmi_3b", "psllw", "mmi_3d", "psrlw", "psraw" /* 0x38 - 0x3f */ }
108
109 #define MMI0_NAMES { \
110 "paddw", "psubw", "pcgtw", "pmaxw", /* 0x00 - 0x03 */ \
111 "paddh", "psubh", "pcgth", "pmaxh", /* 0x04 - 0x07 */ \
112 "paddb", "psubb", "pcgtb", "mmi0_0b", /* 0x08 - 0x0b */ \
113 "mmi0_0c", "mmi0_0d", "mmi0_0e", "mmi0_0f", /* 0x0c - 0x0f */ \
114 "paddsw", "psubsw", "pextlw", "ppacw", /* 0x10 - 0x13 */ \
115 "paddsh", "psubsh", "pextlh", "ppach", /* 0x14 - 0x17 */ \
116 "paddsb", "psubsb", "pextlb", "ppacb", /* 0x18 - 0x1b */ \
117 "mmi0_1c", "mmi0_1d", "pext5", "ppac5" /* 0x1c - 0x1f */ }
118
119 #define MMI1_NAMES { \
120 "mmi1_00", "pabsw", "pceqw", "pminw", /* 0x00 - 0x03 */ \
121 "padsbh", "pabsh", "pceqh", "pminh", /* 0x04 - 0x07 */ \
122 "mmi1_08", "mmi1_09", "pceqb", "mmi1_0b", /* 0x08 - 0x0b */ \
123 "mmi1_0c", "mmi1_0d", "mmi1_0e", "mmi1_0f", /* 0x0c - 0x0f */ \
124 "padduw", "psubuw", "pextuw", "mmi1_13", /* 0x10 - 0x13 */ \
125 "padduh", "psubuh", "pextuh", "mmi1_17", /* 0x14 - 0x17 */ \
126 "paddub", "psubub", "pextub", "qfsrv", /* 0x18 - 0x1b */ \
127 "mmi1_1c", "mmi1_1d", "mmi1_1e", "mmi1_1f" /* 0x1c - 0x1f */ }
128
129 #define MMI2_NAMES { \
130 "pmaddw", "mmi2_01", "psllvw", "psrlvw", /* 0x00 - 0x03 */ \
131 "pmsubw", "mmi2_05", "mmi2_06", "mmi2_07", /* 0x04 - 0x07 */ \
132 "pmfhi", "pmflo", "pinth", "mmi2_0b", /* 0x08 - 0x0b */ \
133 "pmultw", "pdivw", "pcpyld" , "mmi2_0f", /* 0x0c - 0x0f */ \
134 "pmaddh", "phmadh", "pand", "pxor", /* 0x10 - 0x13 */ \
135 "pmsubh", "phmsbh", "mmi2_16", "mmi2_17", /* 0x14 - 0x17 */ \
136 "mmi2_18", "mmi2_19", "pexeh", "prevh", /* 0x18 - 0x1b */ \
137 "pmulth", "pdivbw", "pexew", "prot3w" /* 0x1c - 0x1f */ }
138
139 #define MMI3_NAMES { \
140 "pmadduw", "mmi3_01", "mmi3_02", "psravw", /* 0x00 - 0x03 */ \
141 "mmi3_04", "mmi3_05", "mmi3_06", "mmi3_07", /* 0x04 - 0x07 */ \
142 "pmthi", "pmtlo", "pinteh", "mmi3_0b", /* 0x08 - 0x0b */ \
143 "pmultuw", "pdivuw", "pcpyud" , "mmi3_0f", /* 0x0c - 0x0f */ \
144 "mmi3_10", "mmi3_11", "por", "pnor", /* 0x10 - 0x13 */ \
145 "mmi3_14", "mmi3_15", "mmi3_16", "mmi3_17", /* 0x14 - 0x17 */ \
146 "mmi3_18", "mmi3_19", "pexch", "pcpyh", /* 0x18 - 0x1b */ \
147 "mmi3_1c", "mmi3_1d", "pexcw", "mmi3_1f" /* 0x1c - 0x1f */ }
148
149 #define SPECIAL3_NAMES { \
150 "ext", "dextm", "dextu", "dext", "ins", "dinsm", "dinsu", "dins", /* 0x00 - 0x07 */ \
151 "special3_08", "special3_09", "special3_0a", "special3_0b", "special3_0c", "special3_0d", "special3_0e", "special3_0f", /* 0x08 - 0x0f */ \
152 "special3_10", "special3_11", "special3_12", "special3_13", "special3_14", "special3_15", "special3_16", "special3_17", /* 0x10 - 0x17 */ \
153 "special3_18", "special3_19", "special3_1a", "special3_1b", "special3_1c", "special3_1d", "special3_1e", "special3_1f", /* 0x18 - 0x1f */ \
154 "bshfl", "special3_21", "special3_22", "special3_23", "dbshfl", "special3_25", "special3_26", "special3_27", /* 0x20 - 0x27 */ \
155 "special3_28", "special3_29", "special3_2a", "special3_2b", "special3_2c", "special3_2d", "special3_2e", "special3_2f", /* 0x28 - 0x2f */ \
156 "special3_30", "special3_31", "special3_32", "special3_33", "special3_34", "special3_35", "special3_36", "special3_37", /* 0x30 - 0x37 */ \
157 "special3_38", "special3_39", "special3_3a", "rdhwr", "special3_3c", "special3_3d", "special3_3e", "special3_3f" /* 0x38 - 0x3f */ }
158
159 #define HI6_SPECIAL 0x00 /* 000000 */
160 #define SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */
161 /* 0x01 000001 */
162 #define SPECIAL_SRL 0x02 /* 000010 */ /* MIPS I */
163 #define SPECIAL_SRA 0x03 /* 000011 */ /* MIPS I */
164 #define SPECIAL_SLLV 0x04 /* 000100 */ /* MIPS I */
165 /* 0x05 000101 */
166 #define SPECIAL_SRLV 0x06 /* 000110 */
167 #define SPECIAL_SRAV 0x07 /* 000111 */ /* MIPS I */
168 #define SPECIAL_JR 0x08 /* 001000 */ /* MIPS I */
169 #define SPECIAL_JALR 0x09 /* 001001 */ /* MIPS I */
170 #define SPECIAL_MOVZ 0x0a /* 001010 */ /* MIPS IV */
171 #define SPECIAL_MOVN 0x0b /* 001011 */ /* MIPS IV */
172 #define SPECIAL_SYSCALL 0x0c /* 001100 */ /* MIPS I */
173 #define SPECIAL_BREAK 0x0d /* 001101 */ /* MIPS I */
174 /* 0x0e 001110 */
175 #define SPECIAL_SYNC 0x0f /* 001111 */ /* MIPS II */
176 #define SPECIAL_MFHI 0x10 /* 010000 */ /* MIPS I */
177 #define SPECIAL_MTHI 0x11 /* 010001 */ /* MIPS I */
178 #define SPECIAL_MFLO 0x12 /* 010010 */ /* MIPS I */
179 #define SPECIAL_MTLO 0x13 /* 010011 */ /* MIPS I */
180 #define SPECIAL_DSLLV 0x14 /* 010100 */
181 /* 0x15 010101 */
182 #define SPECIAL_DSRLV 0x16 /* 010110 */ /* MIPS III */
183 #define SPECIAL_DSRAV 0x17 /* 010111 */ /* MIPS III */
184 #define SPECIAL_MULT 0x18 /* 011000 */ /* MIPS I */
185 #define SPECIAL_MULTU 0x19 /* 011001 */ /* MIPS I */
186 #define SPECIAL_DIV 0x1a /* 011010 */ /* MIPS I */
187 #define SPECIAL_DIVU 0x1b /* 011011 */ /* MIPS I */
188 #define SPECIAL_DMULT 0x1c /* 011100 */ /* MIPS III */
189 #define SPECIAL_DMULTU 0x1d /* 011101 */ /* MIPS III */
190 #define SPECIAL_DDIV 0x1e /* 011110 */ /* MIPS III */
191 #define SPECIAL_DDIVU 0x1f /* 011111 */ /* MIPS III */
192 #define SPECIAL_ADD 0x20 /* 100000 */ /* MIPS I */
193 #define SPECIAL_ADDU 0x21 /* 100001 */ /* MIPS I */
194 #define SPECIAL_SUB 0x22 /* 100010 */ /* MIPS I */
195 #define SPECIAL_SUBU 0x23 /* 100011 */ /* MIPS I */
196 #define SPECIAL_AND 0x24 /* 100100 */ /* MIPS I */
197 #define SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */
198 #define SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */
199 #define SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */
200 #define SPECIAL_MFSA 0x28 /* 101000 */ /* R5900/TX79/C790 */
201 #define SPECIAL_MTSA 0x29 /* 101001 */ /* R5900/TX79/C790 */
202 #define SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */
203 #define SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */
204 #define SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */
205 #define SPECIAL_DADDU 0x2d /* 101101 */ /* MIPS III */
206 #define SPECIAL_DSUB 0x2e /* 101110 */
207 #define SPECIAL_DSUBU 0x2f /* 101111 */ /* MIPS III */
208 #define SPECIAL_TGE 0x30 /* 110000 */
209 #define SPECIAL_TGEU 0x31 /* 110001 */
210 #define SPECIAL_TLT 0x32 /* 110010 */
211 #define SPECIAL_TLTU 0x33 /* 110011 */
212 #define SPECIAL_TEQ 0x34 /* 110100 */
213 /* 0x35 110101 */
214 #define SPECIAL_TNE 0x36 /* 110110 */
215 /* 0x37 110111 */
216 #define SPECIAL_DSLL 0x38 /* 111000 */ /* MIPS III */
217 /* 0x39 111001 */
218 #define SPECIAL_DSRL 0x3a /* 111010 */ /* MIPS III */
219 #define SPECIAL_DSRA 0x3b /* 111011 */ /* MIPS III */
220 #define SPECIAL_DSLL32 0x3c /* 111100 */ /* MIPS III */
221 /* 0x3d 111101 */
222 #define SPECIAL_DSRL32 0x3e /* 111110 */ /* MIPS III */
223 #define SPECIAL_DSRA32 0x3f /* 111111 */ /* MIPS III */
224
225 #define HI6_REGIMM 0x01 /* 000001 */
226 #define REGIMM_BLTZ 0x00 /* 00000 */ /* MIPS I */
227 #define REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */
228 #define REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */
229 #define REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */
230 #define REGIMM_TGEI 0x08 /* 01000 */
231 #define REGIMM_TGEIU 0x09 /* 01001 */
232 #define REGIMM_TLTI 0x0a /* 01010 */
233 #define REGIMM_TLTIU 0x0b /* 01011 */
234 #define REGIMM_TEQI 0x0c /* 01100 */
235 #define REGIMM_TNEI 0x0e /* 01110 */
236 #define REGIMM_BLTZAL 0x10 /* 10000 */
237 #define REGIMM_BGEZAL 0x11 /* 10001 */
238 #define REGIMM_BLTZALL 0x12 /* 10010 */
239 #define REGIMM_BGEZALL 0x13 /* 10011 */
240 #define REGIMM_MTSAB 0x18 /* 11000 */ /* R5900/TX79/C790 */
241 #define REGIMM_MTSAH 0x19 /* 11001 */ /* R5900/TX79/C790 */
242 #define REGIMM_SYNCI 0x1f /* 11111 */
243 /* regimm ............... */
244
245 #define HI6_J 0x02 /* 000010 */ /* MIPS I */
246 #define HI6_JAL 0x03 /* 000011 */ /* MIPS I */
247 #define HI6_BEQ 0x04 /* 000100 */ /* MIPS I */
248 #define HI6_BNE 0x05 /* 000101 */
249 #define HI6_BLEZ 0x06 /* 000110 */ /* MIPS I */
250 #define HI6_BGTZ 0x07 /* 000111 */ /* MIPS I */
251 #define HI6_ADDI 0x08 /* 001000 */ /* MIPS I */
252 #define HI6_ADDIU 0x09 /* 001001 */ /* MIPS I */
253 #define HI6_SLTI 0x0a /* 001010 */ /* MIPS I */
254 #define HI6_SLTIU 0x0b /* 001011 */ /* MIPS I */
255 #define HI6_ANDI 0x0c /* 001100 */ /* MIPS I */
256 #define HI6_ORI 0x0d /* 001101 */ /* MIPS I */
257 #define HI6_XORI 0x0e /* 001110 */ /* MIPS I */
258 #define HI6_LUI 0x0f /* 001111 */ /* MIPS I */
259 #define HI6_COP0 0x10 /* 010000 */
260 #define COPz_MFCz 0x00 /* 00000 */
261 #define COPz_DMFCz 0x01 /* 00001 */
262 #define COPz_MTCz 0x04 /* 00100 */
263 #define COPz_DMTCz 0x05 /* 00101 */
264 /*
265 * For cop1 (the floating point coprocessor), if bits 25..21 are
266 * a valid format, then bits 5..0 are the math opcode.
267 *
268 * Otherwise, bits 25..21 are the main coprocessor opcode.
269 */
270 #define COPz_CFCz 0x02 /* 00010 */ /* MIPS I */
271 #define COPz_CTCz 0x06 /* 00110 */ /* MIPS I */
272 #define COPz_BCzc 0x08 /* 01000 */
273 #define COPz_MFMCz 0x0b /* 01011 */
274 #define COP1_FMT_S 0x10 /* 10000 */
275 #define COP1_FMT_D 0x11 /* 10001 */
276 #define COP1_FMT_W 0x14 /* 10100 */
277 #define COP1_FMT_L 0x15 /* 10101 */
278 #define COP1_FMT_PS 0x16 /* 10110 */
279 /* COP0 opcodes = bits 7..0 (only if COP0 and CO=1): */
280 #define COP0_TLBR 0x01 /* 000001 */
281 #define COP0_TLBWI 0x02 /* 000010 */
282 #define COP0_TLBWR 0x06 /* 000110 */
283 #define COP0_TLBP 0x08 /* 001000 */
284 #define COP0_RFE 0x10 /* 010000 */
285 #define COP0_ERET 0x18 /* 011000 */
286 #define COP0_DERET 0x1f /* 011111 */ /* EJTAG */
287 #define COP0_WAIT 0x20 /* 100000 */ /* MIPS32/64 */
288 #define COP0_STANDBY 0x21 /* 100001 */
289 #define COP0_SUSPEND 0x22 /* 100010 */
290 #define COP0_HIBERNATE 0x23 /* 100011 */
291 #define COP0_EI 0x38 /* 111000 */ /* R5900/TX79/C790 */
292 #define COP0_DI 0x39 /* 111001 */ /* R5900/TX79/C790 */
293 #define HI6_COP1 0x11 /* 010001 */
294 #define HI6_COP2 0x12 /* 010010 */
295 #define HI6_COP3 0x13 /* 010011 */
296 #define HI6_BEQL 0x14 /* 010100 */ /* MIPS II */
297 #define HI6_BNEL 0x15 /* 010101 */
298 #define HI6_BLEZL 0x16 /* 010110 */ /* MIPS II */
299 #define HI6_BGTZL 0x17 /* 010111 */ /* MIPS II */
300 #define HI6_DADDI 0x18 /* 011000 */ /* MIPS III */
301 #define HI6_DADDIU 0x19 /* 011001 */ /* MIPS III */
302 #define HI6_LDL 0x1a /* 011010 */ /* MIPS III */
303 #define HI6_LDR 0x1b /* 011011 */ /* MIPS III */
304 #define HI6_SPECIAL2 0x1c /* 011100 */
305 #define SPECIAL2_MADD 0x00 /* 000000 */ /* MIPS32 (?) TODO */
306 #define SPECIAL2_MADDU 0x01 /* 000001 */ /* MIPS32 (?) TODO */
307 #define SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */
308 #define SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */
309 #define SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */
310 #define SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */
311 #define SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */
312 #define SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */
313 #define SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */
314 #define SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */
315 /* MMI (R5900, TX79/C790) occupies the same opcode space as SPECIAL2: */
316 #define MMI_MADD 0x00
317 #define MMI_MADDU 0x01
318 #define MMI_PLZCW 0x04
319 #define MMI_MMI0 0x08
320 #define MMI0_PADDW 0x00
321 #define MMI0_PSUBW 0x01
322 #define MMI0_PCGTW 0x02
323 #define MMI0_PMAXW 0x03
324 #define MMI0_PADDH 0x04
325 #define MMI0_PSUBH 0x05
326 #define MMI0_PCGTH 0x06
327 #define MMI0_PMAXH 0x07
328 #define MMI0_PADDB 0x08
329 #define MMI0_PSUBB 0x09
330 #define MMI0_PCGTB 0x0a
331 #define MMI0_PADDSW 0x10
332 #define MMI0_PSUBSW 0x11
333 #define MMI0_PEXTLW 0x12
334 #define MMI0_PPACW 0x13
335 #define MMI0_PADDSH 0x14
336 #define MMI0_PSUBSH 0x15
337 #define MMI0_PEXTLH 0x16
338 #define MMI0_PPACH 0x17
339 #define MMI0_PADDSB 0x18
340 #define MMI0_PSUBSB 0x19
341 #define MMI0_PEXTLB 0x1a
342 #define MMI0_PPACB 0x1b
343 #define MMI0_PEXT5 0x1e
344 #define MMI0_PPAC5 0x1f
345 #define MMI_MMI2 0x09
346 #define MMI2_PMADDW 0x00
347 #define MMI2_PSLLVW 0x02
348 #define MMI2_PSRLVW 0x03
349 #define MMI2_PMSUBW 0x04
350 #define MMI2_PMFHI 0x08
351 #define MMI2_PMFLO 0x09
352 #define MMI2_PINTH 0x0a
353 #define MMI2_PMULTW 0x0c
354 #define MMI2_PDIVW 0x0d
355 #define MMI2_PCPYLD 0x0e
356 #define MMI2_PMADDH 0x10
357 #define MMI2_PHMADH 0x11
358 #define MMI2_PAND 0x12
359 #define MMI2_PXOR 0x13
360 #define MMI2_PMSUBH 0x14
361 #define MMI2_PHMSBH 0x15
362 #define MMI2_PEXEH 0x1a
363 #define MMI2_PREVH 0x1b
364 #define MMI2_PMULTH 0x1c
365 #define MMI2_PDIVBW 0x1d
366 #define MMI2_PEXEW 0x1e
367 #define MMI2_PROT3W 0x1f
368 #define MMI_MFHI1 0x10
369 #define MMI_MTHI1 0x11
370 #define MMI_MFLO1 0x12
371 #define MMI_MTLO1 0x13
372 #define MMI_MULT1 0x18
373 #define MMI_MULTU1 0x19
374 #define MMI_DIV1 0x1a
375 #define MMI_DIVU1 0x1b
376 #define MMI_MADD1 0x20
377 #define MMI_MADDU1 0x21
378 #define MMI_MMI1 0x28
379 #define MMI1_PABSW 0x01
380 #define MMI1_PCEQW 0x02
381 #define MMI1_PMINW 0x03
382 #define MMI1_PADSBH 0x04
383 #define MMI1_PABSH 0x05
384 #define MMI1_PCEQH 0x06
385 #define MMI1_PMINH 0x07
386 #define MMI1_PCEQB 0x0a
387 #define MMI1_PADDUW 0x10
388 #define MMI1_PSUBUW 0x11
389 #define MMI1_PEXTUW 0x12
390 #define MMI1_PADDUH 0x14
391 #define MMI1_PSUBUH 0x15
392 #define MMI1_PEXTUH 0x16
393 #define MMI1_PADDUB 0x18
394 #define MMI1_PSUBUB 0x19
395 #define MMI1_PEXTUB 0x1a
396 #define MMI1_QFSRV 0x1b
397 #define MMI_MMI3 0x29
398 #define MMI3_PMADDUW 0x00
399 #define MMI3_PSRAVW 0x03
400 #define MMI3_PMTHI 0x08
401 #define MMI3_PMTLO 0x09
402 #define MMI3_PINTEH 0x0a
403 #define MMI3_PMULTUW 0x0c
404 #define MMI3_PDIVUW 0x0d
405 #define MMI3_PCPYUD 0x0e
406 #define MMI3_POR 0x12
407 #define MMI3_PNOR 0x13
408 #define MMI3_PEXCH 0x1a
409 #define MMI3_PCPYH 0x1b
410 #define MMI3_PEXCW 0x1e
411 #define MMI_PMFHL 0x30
412 #define MMI_PMTHL 0x31
413 #define MMI_PSLLH 0x34
414 #define MMI_PSRLH 0x36
415 #define MMI_PSRAH 0x37
416 #define MMI_PSLLW 0x3c
417 #define MMI_PSRLW 0x3e
418 #define MMI_PSRAW 0x3f
419 /* JALX (TODO) 0x1d 011101 */
420 #define HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */
421 /* TODO: MDMX opcodes */
422 #define HI6_SQ_SPECIAL3 0x1f /* 011111 */ /* sq on R5900, SPECIAL3 on MIPS32/64 rev 2 */
423 #define SPECIAL3_EXT 0x00 /* 000000 */
424 #define SPECIAL3_DEXTM 0x01 /* 000001 */
425 #define SPECIAL3_DEXTU 0x02 /* 000010 */
426 #define SPECIAL3_DEXT 0x03 /* 000011 */
427 #define SPECIAL3_INS 0x04 /* 000100 */
428 #define SPECIAL3_DINSM 0x05 /* 000101 */
429 #define SPECIAL3_DINSU 0x06 /* 000110 */
430 #define SPECIAL3_DINS 0x07 /* 000111 */
431 #define SPECIAL3_BSHFL 0x20 /* 100000 */
432 #define BSHFL_WSBH 0x02 /* 00010 */
433 #define SPECIAL3_DBSHFL 0x24 /* 100100 */
434 #define SPECIAL3_RDHWR 0x3b /* 111011 */
435 #define HI6_LB 0x20 /* 100000 */ /* MIPS I */
436 #define HI6_LH 0x21 /* 100001 */ /* MIPS I */
437 #define HI6_LWL 0x22 /* 100010 */ /* MIPS I */
438 #define HI6_LW 0x23 /* 100011 */ /* MIPS I */
439 #define HI6_LBU 0x24 /* 100100 */ /* MIPS I */
440 #define HI6_LHU 0x25 /* 100101 */ /* MIPS I */
441 #define HI6_LWR 0x26 /* 100110 */ /* MIPS I */
442 #define HI6_LWU 0x27 /* 100111 */ /* MIPS III */
443 #define HI6_SB 0x28 /* 101000 */ /* MIPS I */
444 #define HI6_SH 0x29 /* 101001 */ /* MIPS I */
445 #define HI6_SWL 0x2a /* 101010 */ /* MIPS I */
446 #define HI6_SW 0x2b /* 101011 */ /* MIPS I */
447 #define HI6_SDL 0x2c /* 101100 */ /* MIPS III */
448 #define HI6_SDR 0x2d /* 101101 */ /* MIPS III */
449 #define HI6_SWR 0x2e /* 101110 */ /* MIPS I */
450 #define HI6_CACHE 0x2f /* 101111 */ /* ??? R4000 */
451 #define HI6_LL 0x30 /* 110000 */ /* MIPS II */
452 #define HI6_LWC1 0x31 /* 110001 */ /* MIPS I */
453 #define HI6_LWC2 0x32 /* 110010 */ /* MIPS I */
454 #define HI6_LWC3 0x33 /* 110011 */ /* MIPS I */
455 #define HI6_LLD 0x34 /* 110100 */ /* MIPS III */
456 #define HI6_LDC1 0x35 /* 110101 */ /* MIPS II */
457 #define HI6_LDC2 0x36 /* 110110 */ /* MIPS II */
458 #define HI6_LD 0x37 /* 110111 */ /* MIPS III */
459 #define HI6_SC 0x38 /* 111000 */ /* MIPS II */
460 #define HI6_SWC1 0x39 /* 111001 */ /* MIPS I */
461 #define HI6_SWC2 0x3a /* 111010 */ /* MIPS I */
462 #define HI6_SWC3 0x3b /* 111011 */ /* MIPS I */
463 #define HI6_SCD 0x3c /* 111100 */ /* MIPS III */
464 #define HI6_SDC1 0x3d /* 111101 */ /* MIPS II */
465 #define HI6_SDC2 0x3e /* 111110 */ /* MIPS II */
466 #define HI6_SD 0x3f /* 111111 */ /* MIPS III */
467
468
469 #endif /* OPCODES_MIPS_H */
  ViewVC Help
Powered by ViewVC 1.1.26