/[gxemul]/trunk/src/include/opcodes_mips.h
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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 5 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 #ifndef OPCODES_MIPS_H
2 #define OPCODES_MIPS_H
3
4 /*
5 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: opcodes_mips.h,v 1.16 2006/12/30 13:31:01 debug Exp $
32 *
33 * MIPS opcodes, gathered from various sources.
34 *
35 * There are quite a number of different MIPS instruction sets, some are
36 * subsets/supersets of others, but not all of them.
37 *
38 * MIPS ISA I, II, III, IV: Backward-compatible ISAs used in R2000/R3000
39 * (ISA I), R6000 (ISA II), R4000 (ISA III),
40 * and R5000/R1x000 (ISA IV).
41 *
42 * MIPS ISA V: Never implemented in hardware?
43 *
44 * MIPS32 and MIPS64: The "modern" version of the ISA. These exist
45 * in a revision 1, and a revision 2 (the latest
46 * at the time of writing this).
47 *
48 * MIPS16: A special encoding form for MIPS32/64 which
49 * uses 16-bit instruction words instead of
50 * 32-bit.
51 *
52 * MDMX: MIPS Digital Media Extension.
53 *
54 * MIPS 3D: 3D instructions.
55 *
56 * MIPS MT: Multi-Threaded stuff.
57 */
58
59
60 /* Opcodes: */
61
62 #define HI6_NAMES { \
63 "special", "regimm", "j", "jal", "beq", "bne", "blez", "bgtz", /* 0x00 - 0x07 */ \
64 "addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui", /* 0x08 - 0x0f */ \
65 "cop0", "cop1", "cop2", "cop3", "beql", "bnel", "blezl", "bgtzl", /* 0x10 - 0x17 */ \
66 "daddi", "daddiu", "ldl", "ldr", "special2", "hi6_1d","lq" /*mdmx*/, "sq" /*special3*/, /* 0x18 - 0x1f */\
67 "lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "lwu", /* 0x20 - 0x27 */ \
68 "sb", "sh", "swl", "sw", "sdl", "sdr", "swr", "cache", /* 0x28 - 0x2f */ \
69 "ll", "lwc1", "lwc2", "lwc3", "lld", "ldc1", "ldc2", "ld", /* 0x30 - 0x37 */ \
70 "sc", "swc1", "swc2", "swc3", "scd", "sdc1", "sdc2", "sd" /* 0x38 - 0x3f */ }
71
72 #define REGIMM_NAMES { \
73 "bltz", "bgez", "bltzl", "bgezl", "regimm_04", "regimm_05", "regimm_06", "regimm_07", /* 0x00 - 0x07 */ \
74 "tgei", "tgeiu", "tlti", "tltiu", "teqi", "regimm_0d", "tnei", "regimm_0f", /* 0x08 - 0x0f */ \
75 "bltzal", "bgezal", "bltzall", "bgezall", "regimm_14", "regimm_15", "regimm_16", "regimm_17", /* 0x10 - 0x17 */ \
76 "mtsab", "mtsah", "regimm_1a", "regimm_1b", "regimm_1c", "regimm_1d", "regimm_1e", "synci" /* 0x18 - 0x1f */ }
77
78 #define SPECIAL_NAMES { \
79 "sll", "special_01", "srl", "sra", "sllv", "special_05", "srlv", "srav", /* 0x00 - 0x07 */ \
80 "jr", "jalr", "movz", "movn", "syscall","break", "special_0e", "sync", /* 0x08 - 0x0f */ \
81 "mfhi", "mthi", "mflo", "mtlo", "dsllv", "special_15", "dsrlv", "dsrav", /* 0x10 - 0x17 */ \
82 "mult", "multu", "div", "divu", "dmult", "dmultu", "ddiv", "ddivu", /* 0x18 - 0x1f */ \
83 "add", "addu", "sub", "subu", "and", "or", "xor", "nor", /* 0x20 - 0x27 */ \
84 "special_28","special_29","slt", "sltu", "dadd", "daddu", "dsub", "dsubu", /* 0x28 - 0x2f */ \
85 "tge", "tgeu", "tlt", "tltu", "teq", "special_35", "tne", "special_37",/* 0x30 - 0x37 */ \
86 "dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32" /* 0x38 - 0x3f */ }
87
88 /* SPECIAL opcodes, when the rotate bit is set: */
89 #define SPECIAL_ROT_NAMES { \
90 "rot_00", "rot_01", "ror", "rot_03", "rot_04", "rot_05", "rorv", "rot_07", /* 0x00 - 0x07 */ \
91 "rot_08", "rot_09", "rot_0a", "rot_0b", "rot_0c", "rot_0d", "rot_0e", "rot_0f", /* 0x08 - 0x0f */ \
92 "rot_10", "rot_11", "rot_12", "rot_13", "rot_14", "rot_15", "drorv", "rot_17", /* 0x10 - 0x17 */ \
93 "rot_18", "rot_19", "rot_1a", "rot_1b", "rot_1c", "rot_1d", "rot_1e", "rot_1f", /* 0x18 - 0x1f */ \
94 "rot_20", "rot_21", "rot_22", "rot_23", "rot_24", "rot_25", "rot_26", "rot_27", /* 0x20 - 0x27 */ \
95 "rot_28", "rot_29", "rot_2a", "rot_2b", "rot_2c", "rot_2d", "rot_2e", "rot_2f", /* 0x28 - 0x2f */ \
96 "rot_30", "rot_31", "rot_32", "rot_33", "rot_34", "rot_35", "rot_36", "rot_37", /* 0x30 - 0x37 */ \
97 "rot_38", "rot_39", "dror", "rot_3b", "rot_3c", "rot_3d", "dror32", "rot_3f" /* 0x38 - 0x3f */ }
98
99 #define SPECIAL2_NAMES { \
100 "madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \
101 "special2_08", "special2_09", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \
102 "special2_10", "special2_11", "special2_12", "special2_13", "special2_14", "special2_15", "special2_16", "special2_17", /* 0x10 - 0x17 */ \
103 "special2_18", "special2_19", "special2_1a", "special2_1b", "special2_1c", "special2_1d", "special2_1e", "special2_1f", /* 0x18 - 0x1f */ \
104 "clz", "clo", "special2_22", "special2_23", "dclz", "dclo", "special2_26", "special2_27", /* 0x20 - 0x27 */ \
105 "special2_28", "special2_29", "special2_2a", "special2_2b", "special2_2c", "special2_2d", "special2_2e", "special2_2f", /* 0x28 - 0x2f */ \
106 "special2_30", "special2_31", "special2_32", "special2_33", "special2_34", "special2_35", "special2_36", "special2_37", /* 0x30 - 0x37 */ \
107 "special2_38", "special2_39", "special2_3a", "special2_3b", "special2_3c", "special2_3d", "special2_3e", "sdbbp" /* 0x38 - 0x3f */ }
108
109 /* MMI (on R5900, TX79/C790) occupies the same space as SPECIAL2 */
110 #define MMI_NAMES { \
111 "madd", "maddu", "mmi_02", "mmi_03", "plzcw", "mmi_05", "mmi_06", "mmi_07", /* 0x00 - 0x07 */ \
112 "mmi0", "mmi2", "mmi_0a", "mmi_0b", "mmi_0c", "mmi_0d", "mmi_0e", "mmi_0f", /* 0x08 - 0x0f */ \
113 "mfhi1", "mthi1", "mflo1", "mtlo1", "mmi_14", "mmi_15", "mmi_16", "mmi_17", /* 0x10 - 0x17 */ \
114 "mult1", "multu1", "div1", "divu1", "mmi_1c", "mmi_1d", "mmi_1e", "mmi_1f", /* 0x18 - 0x1f */ \
115 "madd1", "maddu1", "mmi_22", "mmi_23", "mmi_24", "mmi_25", "mmi_26", "mmi_27", /* 0x20 - 0x27 */ \
116 "mmi1", "mmi3", "mmi_2a", "mmi_2b", "mmi_2c", "mmi_2d", "mmi_2e", "mmi_2f", /* 0x28 - 0x2f */ \
117 "pmfhl", "pmthl", "mmi_32", "mmi_33", "psllh", "mmi_35", "psrlh", "psrah", /* 0x30 - 0x37 */ \
118 "mmi_38", "mmi_39", "mmi_3a", "mmi_3b", "psllw", "mmi_3d", "psrlw", "psraw" /* 0x38 - 0x3f */ }
119
120 #define MMI0_NAMES { \
121 "paddw", "psubw", "pcgtw", "pmaxw", /* 0x00 - 0x03 */ \
122 "paddh", "psubh", "pcgth", "pmaxh", /* 0x04 - 0x07 */ \
123 "paddb", "psubb", "pcgtb", "mmi0_0b", /* 0x08 - 0x0b */ \
124 "mmi0_0c", "mmi0_0d", "mmi0_0e", "mmi0_0f", /* 0x0c - 0x0f */ \
125 "paddsw", "psubsw", "pextlw", "ppacw", /* 0x10 - 0x13 */ \
126 "paddsh", "psubsh", "pextlh", "ppach", /* 0x14 - 0x17 */ \
127 "paddsb", "psubsb", "pextlb", "ppacb", /* 0x18 - 0x1b */ \
128 "mmi0_1c", "mmi0_1d", "pext5", "ppac5" /* 0x1c - 0x1f */ }
129
130 #define MMI1_NAMES { \
131 "mmi1_00", "pabsw", "pceqw", "pminw", /* 0x00 - 0x03 */ \
132 "padsbh", "pabsh", "pceqh", "pminh", /* 0x04 - 0x07 */ \
133 "mmi1_08", "mmi1_09", "pceqb", "mmi1_0b", /* 0x08 - 0x0b */ \
134 "mmi1_0c", "mmi1_0d", "mmi1_0e", "mmi1_0f", /* 0x0c - 0x0f */ \
135 "padduw", "psubuw", "pextuw", "mmi1_13", /* 0x10 - 0x13 */ \
136 "padduh", "psubuh", "pextuh", "mmi1_17", /* 0x14 - 0x17 */ \
137 "paddub", "psubub", "pextub", "qfsrv", /* 0x18 - 0x1b */ \
138 "mmi1_1c", "mmi1_1d", "mmi1_1e", "mmi1_1f" /* 0x1c - 0x1f */ }
139
140 #define MMI2_NAMES { \
141 "pmaddw", "mmi2_01", "psllvw", "psrlvw", /* 0x00 - 0x03 */ \
142 "pmsubw", "mmi2_05", "mmi2_06", "mmi2_07", /* 0x04 - 0x07 */ \
143 "pmfhi", "pmflo", "pinth", "mmi2_0b", /* 0x08 - 0x0b */ \
144 "pmultw", "pdivw", "pcpyld" , "mmi2_0f", /* 0x0c - 0x0f */ \
145 "pmaddh", "phmadh", "pand", "pxor", /* 0x10 - 0x13 */ \
146 "pmsubh", "phmsbh", "mmi2_16", "mmi2_17", /* 0x14 - 0x17 */ \
147 "mmi2_18", "mmi2_19", "pexeh", "prevh", /* 0x18 - 0x1b */ \
148 "pmulth", "pdivbw", "pexew", "prot3w" /* 0x1c - 0x1f */ }
149
150 #define MMI3_NAMES { \
151 "pmadduw", "mmi3_01", "mmi3_02", "psravw", /* 0x00 - 0x03 */ \
152 "mmi3_04", "mmi3_05", "mmi3_06", "mmi3_07", /* 0x04 - 0x07 */ \
153 "pmthi", "pmtlo", "pinteh", "mmi3_0b", /* 0x08 - 0x0b */ \
154 "pmultuw", "pdivuw", "pcpyud" , "mmi3_0f", /* 0x0c - 0x0f */ \
155 "mmi3_10", "mmi3_11", "por", "pnor", /* 0x10 - 0x13 */ \
156 "mmi3_14", "mmi3_15", "mmi3_16", "mmi3_17", /* 0x14 - 0x17 */ \
157 "mmi3_18", "mmi3_19", "pexch", "pcpyh", /* 0x18 - 0x1b */ \
158 "mmi3_1c", "mmi3_1d", "pexcw", "mmi3_1f" /* 0x1c - 0x1f */ }
159
160 #define SPECIAL3_NAMES { \
161 "ext", "dextm", "dextu", "dext", "ins", "dinsm", "dinsu", "dins", /* 0x00 - 0x07 */ \
162 "special3_08", "special3_09", "special3_0a", "special3_0b", "special3_0c", "special3_0d", "special3_0e", "special3_0f", /* 0x08 - 0x0f */ \
163 "special3_10", "special3_11", "special3_12", "special3_13", "special3_14", "special3_15", "special3_16", "special3_17", /* 0x10 - 0x17 */ \
164 "special3_18", "special3_19", "special3_1a", "special3_1b", "special3_1c", "special3_1d", "special3_1e", "special3_1f", /* 0x18 - 0x1f */ \
165 "bshfl", "special3_21", "special3_22", "special3_23", "dbshfl", "special3_25", "special3_26", "special3_27", /* 0x20 - 0x27 */ \
166 "special3_28", "special3_29", "special3_2a", "special3_2b", "special3_2c", "special3_2d", "special3_2e", "special3_2f", /* 0x28 - 0x2f */ \
167 "special3_30", "special3_31", "special3_32", "special3_33", "special3_34", "special3_35", "special3_36", "special3_37", /* 0x30 - 0x37 */ \
168 "special3_38", "special3_39", "special3_3a", "rdhwr", "special3_3c", "special3_3d", "special3_3e", "special3_3f" /* 0x38 - 0x3f */ }
169
170 #define HI6_SPECIAL 0x00 /* 000000 */
171 #define SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */
172 /* 0x01 000001 */
173 #define SPECIAL_SRL 0x02 /* 000010 */ /* MIPS I */
174 #define SPECIAL_SRA 0x03 /* 000011 */ /* MIPS I */
175 #define SPECIAL_SLLV 0x04 /* 000100 */ /* MIPS I */
176 /* 0x05 000101 */
177 #define SPECIAL_SRLV 0x06 /* 000110 */
178 #define SPECIAL_SRAV 0x07 /* 000111 */ /* MIPS I */
179 #define SPECIAL_JR 0x08 /* 001000 */ /* MIPS I */
180 #define SPECIAL_JALR 0x09 /* 001001 */ /* MIPS I */
181 #define SPECIAL_MOVZ 0x0a /* 001010 */ /* MIPS IV */
182 #define SPECIAL_MOVN 0x0b /* 001011 */ /* MIPS IV */
183 #define SPECIAL_SYSCALL 0x0c /* 001100 */ /* MIPS I */
184 #define SPECIAL_BREAK 0x0d /* 001101 */ /* MIPS I */
185 /* 0x0e 001110 */
186 #define SPECIAL_SYNC 0x0f /* 001111 */ /* MIPS II */
187 #define SPECIAL_MFHI 0x10 /* 010000 */ /* MIPS I */
188 #define SPECIAL_MTHI 0x11 /* 010001 */ /* MIPS I */
189 #define SPECIAL_MFLO 0x12 /* 010010 */ /* MIPS I */
190 #define SPECIAL_MTLO 0x13 /* 010011 */ /* MIPS I */
191 #define SPECIAL_DSLLV 0x14 /* 010100 */
192 /* 0x15 010101 */
193 #define SPECIAL_DSRLV 0x16 /* 010110 */ /* MIPS III */
194 #define SPECIAL_DSRAV 0x17 /* 010111 */ /* MIPS III */
195 #define SPECIAL_MULT 0x18 /* 011000 */ /* MIPS I */
196 #define SPECIAL_MULTU 0x19 /* 011001 */ /* MIPS I */
197 #define SPECIAL_DIV 0x1a /* 011010 */ /* MIPS I */
198 #define SPECIAL_DIVU 0x1b /* 011011 */ /* MIPS I */
199 #define SPECIAL_DMULT 0x1c /* 011100 */ /* MIPS III */
200 #define SPECIAL_DMULTU 0x1d /* 011101 */ /* MIPS III */
201 #define SPECIAL_DDIV 0x1e /* 011110 */ /* MIPS III */
202 #define SPECIAL_DDIVU 0x1f /* 011111 */ /* MIPS III */
203 #define SPECIAL_ADD 0x20 /* 100000 */ /* MIPS I */
204 #define SPECIAL_ADDU 0x21 /* 100001 */ /* MIPS I */
205 #define SPECIAL_SUB 0x22 /* 100010 */ /* MIPS I */
206 #define SPECIAL_SUBU 0x23 /* 100011 */ /* MIPS I */
207 #define SPECIAL_AND 0x24 /* 100100 */ /* MIPS I */
208 #define SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */
209 #define SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */
210 #define SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */
211 #define SPECIAL_MFSA 0x28 /* 101000 */ /* R5900/TX79/C790 */
212 #define SPECIAL_MTSA 0x29 /* 101001 */ /* R5900/TX79/C790 */
213 #define SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */
214 #define SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */
215 #define SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */
216 #define SPECIAL_DADDU 0x2d /* 101101 */ /* MIPS III */
217 #define SPECIAL_DSUB 0x2e /* 101110 */
218 #define SPECIAL_DSUBU 0x2f /* 101111 */ /* MIPS III */
219 #define SPECIAL_TGE 0x30 /* 110000 */
220 #define SPECIAL_TGEU 0x31 /* 110001 */
221 #define SPECIAL_TLT 0x32 /* 110010 */
222 #define SPECIAL_TLTU 0x33 /* 110011 */
223 #define SPECIAL_TEQ 0x34 /* 110100 */
224 /* 0x35 110101 */
225 #define SPECIAL_TNE 0x36 /* 110110 */
226 /* 0x37 110111 */
227 #define SPECIAL_DSLL 0x38 /* 111000 */ /* MIPS III */
228 /* 0x39 111001 */
229 #define SPECIAL_DSRL 0x3a /* 111010 */ /* MIPS III */
230 #define SPECIAL_DSRA 0x3b /* 111011 */ /* MIPS III */
231 #define SPECIAL_DSLL32 0x3c /* 111100 */ /* MIPS III */
232 /* 0x3d 111101 */
233 #define SPECIAL_DSRL32 0x3e /* 111110 */ /* MIPS III */
234 #define SPECIAL_DSRA32 0x3f /* 111111 */ /* MIPS III */
235
236 #define HI6_REGIMM 0x01 /* 000001 */
237 #define REGIMM_BLTZ 0x00 /* 00000 */ /* MIPS I */
238 #define REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */
239 #define REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */
240 #define REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */
241 #define REGIMM_TGEI 0x08 /* 01000 */
242 #define REGIMM_TGEIU 0x09 /* 01001 */
243 #define REGIMM_TLTI 0x0a /* 01010 */
244 #define REGIMM_TLTIU 0x0b /* 01011 */
245 #define REGIMM_TEQI 0x0c /* 01100 */
246 #define REGIMM_TNEI 0x0e /* 01110 */
247 #define REGIMM_BLTZAL 0x10 /* 10000 */
248 #define REGIMM_BGEZAL 0x11 /* 10001 */
249 #define REGIMM_BLTZALL 0x12 /* 10010 */
250 #define REGIMM_BGEZALL 0x13 /* 10011 */
251 #define REGIMM_MTSAB 0x18 /* 11000 */ /* R5900/TX79/C790 */
252 #define REGIMM_MTSAH 0x19 /* 11001 */ /* R5900/TX79/C790 */
253 #define REGIMM_SYNCI 0x1f /* 11111 */
254 /* regimm ............... */
255
256 #define HI6_J 0x02 /* 000010 */ /* MIPS I */
257 #define HI6_JAL 0x03 /* 000011 */ /* MIPS I */
258 #define HI6_BEQ 0x04 /* 000100 */ /* MIPS I */
259 #define HI6_BNE 0x05 /* 000101 */
260 #define HI6_BLEZ 0x06 /* 000110 */ /* MIPS I */
261 #define HI6_BGTZ 0x07 /* 000111 */ /* MIPS I */
262 #define HI6_ADDI 0x08 /* 001000 */ /* MIPS I */
263 #define HI6_ADDIU 0x09 /* 001001 */ /* MIPS I */
264 #define HI6_SLTI 0x0a /* 001010 */ /* MIPS I */
265 #define HI6_SLTIU 0x0b /* 001011 */ /* MIPS I */
266 #define HI6_ANDI 0x0c /* 001100 */ /* MIPS I */
267 #define HI6_ORI 0x0d /* 001101 */ /* MIPS I */
268 #define HI6_XORI 0x0e /* 001110 */ /* MIPS I */
269 #define HI6_LUI 0x0f /* 001111 */ /* MIPS I */
270 #define HI6_COP0 0x10 /* 010000 */
271 #define COPz_MFCz 0x00 /* 00000 */
272 #define COPz_DMFCz 0x01 /* 00001 */
273 #define COPz_MTCz 0x04 /* 00100 */
274 #define COPz_DMTCz 0x05 /* 00101 */
275 /*
276 * For cop1 (the floating point coprocessor), if bits 25..21 are
277 * a valid format, then bits 5..0 are the math opcode.
278 *
279 * Otherwise, bits 25..21 are the main coprocessor opcode.
280 */
281 #define COPz_CFCz 0x02 /* 00010 */ /* MIPS I */
282 #define COPz_CTCz 0x06 /* 00110 */ /* MIPS I */
283 #define COPz_BCzc 0x08 /* 01000 */
284 #define COPz_MFMCz 0x0b /* 01011 */
285 #define COP1_FMT_S 0x10 /* 10000 */
286 #define COP1_FMT_D 0x11 /* 10001 */
287 #define COP1_FMT_W 0x14 /* 10100 */
288 #define COP1_FMT_L 0x15 /* 10101 */
289 #define COP1_FMT_PS 0x16 /* 10110 */
290 /* COP0 opcodes = bits 7..0 (only if COP0 and CO=1): */
291 #define COP0_TLBR 0x01 /* 000001 */
292 #define COP0_TLBWI 0x02 /* 000010 */
293 #define COP0_TLBWR 0x06 /* 000110 */
294 #define COP0_TLBP 0x08 /* 001000 */
295 #define COP0_RFE 0x10 /* 010000 */
296 #define COP0_ERET 0x18 /* 011000 */
297 #define COP0_DERET 0x1f /* 011111 */ /* EJTAG */
298 #define COP0_WAIT 0x20 /* 100000 */ /* MIPS32/64 */
299 #define COP0_STANDBY 0x21 /* 100001 */
300 #define COP0_SUSPEND 0x22 /* 100010 */
301 #define COP0_HIBERNATE 0x23 /* 100011 */
302 #define COP0_EI 0x38 /* 111000 */ /* R5900/TX79/C790 */
303 #define COP0_DI 0x39 /* 111001 */ /* R5900/TX79/C790 */
304 #define HI6_COP1 0x11 /* 010001 */
305 #define HI6_COP2 0x12 /* 010010 */
306 #define HI6_COP3 0x13 /* 010011 */
307 #define HI6_BEQL 0x14 /* 010100 */ /* MIPS II */
308 #define HI6_BNEL 0x15 /* 010101 */
309 #define HI6_BLEZL 0x16 /* 010110 */ /* MIPS II */
310 #define HI6_BGTZL 0x17 /* 010111 */ /* MIPS II */
311 #define HI6_DADDI 0x18 /* 011000 */ /* MIPS III */
312 #define HI6_DADDIU 0x19 /* 011001 */ /* MIPS III */
313 #define HI6_LDL 0x1a /* 011010 */ /* MIPS III */
314 #define HI6_LDR 0x1b /* 011011 */ /* MIPS III */
315 #define HI6_SPECIAL2 0x1c /* 011100 */
316 #define SPECIAL2_MADD 0x00 /* 000000 */ /* MIPS32 (?) TODO */
317 #define SPECIAL2_MADDU 0x01 /* 000001 */ /* MIPS32 (?) TODO */
318 #define SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */
319 #define SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */
320 #define SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */
321 #define SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */
322 #define SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */
323 #define SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */
324 #define SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */
325 #define SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */
326 /* MMI (R5900, TX79/C790) occupies the same opcode space as SPECIAL2: */
327 #define MMI_MADD 0x00
328 #define MMI_MADDU 0x01
329 #define MMI_PLZCW 0x04
330 #define MMI_MMI0 0x08
331 #define MMI0_PADDW 0x00
332 #define MMI0_PSUBW 0x01
333 #define MMI0_PCGTW 0x02
334 #define MMI0_PMAXW 0x03
335 #define MMI0_PADDH 0x04
336 #define MMI0_PSUBH 0x05
337 #define MMI0_PCGTH 0x06
338 #define MMI0_PMAXH 0x07
339 #define MMI0_PADDB 0x08
340 #define MMI0_PSUBB 0x09
341 #define MMI0_PCGTB 0x0a
342 #define MMI0_PADDSW 0x10
343 #define MMI0_PSUBSW 0x11
344 #define MMI0_PEXTLW 0x12
345 #define MMI0_PPACW 0x13
346 #define MMI0_PADDSH 0x14
347 #define MMI0_PSUBSH 0x15
348 #define MMI0_PEXTLH 0x16
349 #define MMI0_PPACH 0x17
350 #define MMI0_PADDSB 0x18
351 #define MMI0_PSUBSB 0x19
352 #define MMI0_PEXTLB 0x1a
353 #define MMI0_PPACB 0x1b
354 #define MMI0_PEXT5 0x1e
355 #define MMI0_PPAC5 0x1f
356 #define MMI_MMI2 0x09
357 #define MMI2_PMADDW 0x00
358 #define MMI2_PSLLVW 0x02
359 #define MMI2_PSRLVW 0x03
360 #define MMI2_PMSUBW 0x04
361 #define MMI2_PMFHI 0x08
362 #define MMI2_PMFLO 0x09
363 #define MMI2_PINTH 0x0a
364 #define MMI2_PMULTW 0x0c
365 #define MMI2_PDIVW 0x0d
366 #define MMI2_PCPYLD 0x0e
367 #define MMI2_PMADDH 0x10
368 #define MMI2_PHMADH 0x11
369 #define MMI2_PAND 0x12
370 #define MMI2_PXOR 0x13
371 #define MMI2_PMSUBH 0x14
372 #define MMI2_PHMSBH 0x15
373 #define MMI2_PEXEH 0x1a
374 #define MMI2_PREVH 0x1b
375 #define MMI2_PMULTH 0x1c
376 #define MMI2_PDIVBW 0x1d
377 #define MMI2_PEXEW 0x1e
378 #define MMI2_PROT3W 0x1f
379 #define MMI_MFHI1 0x10
380 #define MMI_MTHI1 0x11
381 #define MMI_MFLO1 0x12
382 #define MMI_MTLO1 0x13
383 #define MMI_MULT1 0x18
384 #define MMI_MULTU1 0x19
385 #define MMI_DIV1 0x1a
386 #define MMI_DIVU1 0x1b
387 #define MMI_MADD1 0x20
388 #define MMI_MADDU1 0x21
389 #define MMI_MMI1 0x28
390 #define MMI1_PABSW 0x01
391 #define MMI1_PCEQW 0x02
392 #define MMI1_PMINW 0x03
393 #define MMI1_PADSBH 0x04
394 #define MMI1_PABSH 0x05
395 #define MMI1_PCEQH 0x06
396 #define MMI1_PMINH 0x07
397 #define MMI1_PCEQB 0x0a
398 #define MMI1_PADDUW 0x10
399 #define MMI1_PSUBUW 0x11
400 #define MMI1_PEXTUW 0x12
401 #define MMI1_PADDUH 0x14
402 #define MMI1_PSUBUH 0x15
403 #define MMI1_PEXTUH 0x16
404 #define MMI1_PADDUB 0x18
405 #define MMI1_PSUBUB 0x19
406 #define MMI1_PEXTUB 0x1a
407 #define MMI1_QFSRV 0x1b
408 #define MMI_MMI3 0x29
409 #define MMI3_PMADDUW 0x00
410 #define MMI3_PSRAVW 0x03
411 #define MMI3_PMTHI 0x08
412 #define MMI3_PMTLO 0x09
413 #define MMI3_PINTEH 0x0a
414 #define MMI3_PMULTUW 0x0c
415 #define MMI3_PDIVUW 0x0d
416 #define MMI3_PCPYUD 0x0e
417 #define MMI3_POR 0x12
418 #define MMI3_PNOR 0x13
419 #define MMI3_PEXCH 0x1a
420 #define MMI3_PCPYH 0x1b
421 #define MMI3_PEXCW 0x1e
422 #define MMI_PMFHL 0x30
423 #define MMI_PMTHL 0x31
424 #define MMI_PSLLH 0x34
425 #define MMI_PSRLH 0x36
426 #define MMI_PSRAH 0x37
427 #define MMI_PSLLW 0x3c
428 #define MMI_PSRLW 0x3e
429 #define MMI_PSRAW 0x3f
430 /* JALX (TODO) 0x1d 011101 */
431 #define HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */
432 /* TODO: MDMX opcodes */
433 #define HI6_SQ_SPECIAL3 0x1f /* 011111 */ /* sq on R5900, SPECIAL3 on MIPS32/64 rev 2 */
434 #define SPECIAL3_EXT 0x00 /* 000000 */
435 #define SPECIAL3_DEXTM 0x01 /* 000001 */
436 #define SPECIAL3_DEXTU 0x02 /* 000010 */
437 #define SPECIAL3_DEXT 0x03 /* 000011 */
438 #define SPECIAL3_INS 0x04 /* 000100 */
439 #define SPECIAL3_DINSM 0x05 /* 000101 */
440 #define SPECIAL3_DINSU 0x06 /* 000110 */
441 #define SPECIAL3_DINS 0x07 /* 000111 */
442 #define SPECIAL3_BSHFL 0x20 /* 100000 */
443 #define BSHFL_WSBH 0x002 /* 00000..00010 */
444 #define BSHFL_SEB 0x010 /* 00000..10000 */
445 #define BSHFL_SEH 0x018 /* 00000..11000 */
446 #define SPECIAL3_DBSHFL 0x24 /* 100100 */
447 #define BSHFL_DSBH 0x002 /* 00000..00010 */
448 #define BSHFL_DSHD 0x005 /* 00000..00101 */
449 #define SPECIAL3_RDHWR 0x3b /* 111011 */
450 #define HI6_LB 0x20 /* 100000 */ /* MIPS I */
451 #define HI6_LH 0x21 /* 100001 */ /* MIPS I */
452 #define HI6_LWL 0x22 /* 100010 */ /* MIPS I */
453 #define HI6_LW 0x23 /* 100011 */ /* MIPS I */
454 #define HI6_LBU 0x24 /* 100100 */ /* MIPS I */
455 #define HI6_LHU 0x25 /* 100101 */ /* MIPS I */
456 #define HI6_LWR 0x26 /* 100110 */ /* MIPS I */
457 #define HI6_LWU 0x27 /* 100111 */ /* MIPS III */
458 #define HI6_SB 0x28 /* 101000 */ /* MIPS I */
459 #define HI6_SH 0x29 /* 101001 */ /* MIPS I */
460 #define HI6_SWL 0x2a /* 101010 */ /* MIPS I */
461 #define HI6_SW 0x2b /* 101011 */ /* MIPS I */
462 #define HI6_SDL 0x2c /* 101100 */ /* MIPS III */
463 #define HI6_SDR 0x2d /* 101101 */ /* MIPS III */
464 #define HI6_SWR 0x2e /* 101110 */ /* MIPS I */
465 #define HI6_CACHE 0x2f /* 101111 */ /* ??? R4000 */
466 #define HI6_LL 0x30 /* 110000 */ /* MIPS II */
467 #define HI6_LWC1 0x31 /* 110001 */ /* MIPS I */
468 #define HI6_LWC2 0x32 /* 110010 */ /* MIPS I */
469 #define HI6_LWC3 0x33 /* 110011 */ /* MIPS I */
470 #define HI6_LLD 0x34 /* 110100 */ /* MIPS III */
471 #define HI6_LDC1 0x35 /* 110101 */ /* MIPS II */
472 #define HI6_LDC2 0x36 /* 110110 */ /* MIPS II */
473 #define HI6_LD 0x37 /* 110111 */ /* MIPS III */
474 #define HI6_SC 0x38 /* 111000 */ /* MIPS II */
475 #define HI6_SWC1 0x39 /* 111001 */ /* MIPS I */
476 #define HI6_SWC2 0x3a /* 111010 */ /* MIPS I */
477 #define HI6_SWC3 0x3b /* 111011 */ /* MIPS I */
478 #define HI6_SCD 0x3c /* 111100 */ /* MIPS III */
479 #define HI6_SDC1 0x3d /* 111101 */ /* MIPS II */
480 #define HI6_SDC2 0x3e /* 111110 */ /* MIPS II */
481 #define HI6_SD 0x3f /* 111111 */ /* MIPS III */
482
483
484 #endif /* OPCODES_MIPS_H */

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