1 |
#ifndef OPCODES_H |
#ifndef OPCODES_MIPS_H |
2 |
#define OPCODES_H |
#define OPCODES_MIPS_H |
3 |
|
|
4 |
/* |
/* |
5 |
* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
6 |
* |
* |
7 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
8 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: opcodes_mips.h,v 1.2 2005/03/15 06:52:15 debug Exp $ |
* $Id: opcodes_mips.h,v 1.15 2006/09/30 05:39:44 debug Exp $ |
32 |
* |
* |
33 |
* MIPS opcodes, gathered from various sources. |
* MIPS opcodes, gathered from various sources. |
34 |
|
* |
35 |
|
* There are quite a number of different MIPS instruction sets, some are |
36 |
|
* subsets/supersets of others, but not all of them. |
37 |
|
* |
38 |
|
* MIPS ISA I, II, III, IV: Backward-compatible ISAs used in R2000/R3000 |
39 |
|
* (ISA I), R6000 (ISA II), R4000 (ISA III), |
40 |
|
* and R5000/R1x000 (ISA IV). |
41 |
|
* |
42 |
|
* MIPS ISA V: Never implemented in hardware? |
43 |
|
* |
44 |
|
* MIPS32 and MIPS64: The "modern" version of the ISA. These exist |
45 |
|
* in a revision 1, and a revision 2 (the latest |
46 |
|
* at the time of writing this). |
47 |
|
* |
48 |
|
* MIPS16: A special encoding form for MIPS32/64 which |
49 |
|
* uses 16-bit instruction words instead of |
50 |
|
* 32-bit. |
51 |
|
* |
52 |
|
* MDMX: MIPS Digital Media Extension. |
53 |
|
* |
54 |
|
* MIPS 3D: 3D instructions. |
55 |
|
* |
56 |
|
* MIPS MT: Multi-Threaded stuff. |
57 |
*/ |
*/ |
58 |
|
|
59 |
|
|
60 |
/* Opcodes: (see page 191 in MIPS_IV_Instruction_Set_v3.2.pdf) */ |
/* Opcodes: */ |
61 |
|
|
62 |
#define HI6_NAMES { \ |
#define HI6_NAMES { \ |
63 |
"special", "regimm", "j", "jal", "beq", "bne", "blez", "bgtz", /* 0x00 - 0x07 */ \ |
"special", "regimm", "j", "jal", "beq", "bne", "blez", "bgtz", /* 0x00 - 0x07 */ \ |
64 |
"addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui", /* 0x08 - 0x0f */ \ |
"addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui", /* 0x08 - 0x0f */ \ |
65 |
"cop0", "cop1", "cop2", "cop3", "beql", "bnel", "blezl", "bgtzl", /* 0x10 - 0x17 */ \ |
"cop0", "cop1", "cop2", "cop3", "beql", "bnel", "blezl", "bgtzl", /* 0x10 - 0x17 */ \ |
66 |
"daddi", "daddiu", "ldl", "ldr", "special2", "opcode_1d", "lq_mdmx", "sq", /* 0x18 - 0x1f */ \ |
"daddi", "daddiu", "ldl", "ldr", "special2", "hi6_1d","lq" /*mdmx*/, "sq" /*special3*/, /* 0x18 - 0x1f */\ |
67 |
"lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "lwu", /* 0x20 - 0x27 */ \ |
"lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "lwu", /* 0x20 - 0x27 */ \ |
68 |
"sb", "sh", "swl", "sw", "sdl", "sdr", "swr", "cache", /* 0x28 - 0x2f */ \ |
"sb", "sh", "swl", "sw", "sdl", "sdr", "swr", "cache", /* 0x28 - 0x2f */ \ |
69 |
"ll", "lwc1", "lwc2", "lwc3", "lld", "ldc1", "ldc2", "ld", /* 0x30 - 0x37 */ \ |
"ll", "lwc1", "lwc2", "lwc3", "lld", "ldc1", "ldc2", "ld", /* 0x30 - 0x37 */ \ |
70 |
"sc", "swc1", "swc2", "swc3", "scd", "sdc1", "sdc2", "sd" /* 0x38 - 0x3f */ } |
"sc", "swc1", "swc2", "swc3", "scd", "sdc1", "sdc2", "sd" /* 0x38 - 0x3f */ } |
71 |
|
|
72 |
#define REGIMM_NAMES { \ |
#define REGIMM_NAMES { \ |
73 |
"bltz", "bgez", "bltzl", "bgezl", "regimm_04", "regimm_05", "regimm_06", "regimm_07", /* 0x00 - 0x07 */ \ |
"bltz", "bgez", "bltzl", "bgezl", "regimm_04", "regimm_05", "regimm_06", "regimm_07", /* 0x00 - 0x07 */ \ |
74 |
"regimm_08", "regimm_09", "regimm_0a", "regimm_0b", "regimm_0c", "regimm_0d", "regimm_0e", "regimm_0f", /* 0x08 - 0x0f */ \ |
"tgei", "tgeiu", "tlti", "tltiu", "teqi", "regimm_0d", "tnei", "regimm_0f", /* 0x08 - 0x0f */ \ |
75 |
"bltzal", "bgezal", "bltzall", "bgezall", "regimm_14", "regimm_15", "regimm_16", "regimm_17", /* 0x10 - 0x17 */ \ |
"bltzal", "bgezal", "bltzall", "bgezall", "regimm_14", "regimm_15", "regimm_16", "regimm_17", /* 0x10 - 0x17 */ \ |
76 |
"regimm_18", "regimm_19", "regimm_1a", "regimm_1b", "regimm_1c", "regimm_1d", "regimm_1e", "regimm_1f" /* 0x18 - 0x1f */ } |
"mtsab", "mtsah", "regimm_1a", "regimm_1b", "regimm_1c", "regimm_1d", "regimm_1e", "synci" /* 0x18 - 0x1f */ } |
77 |
|
|
78 |
#define SPECIAL_NAMES { \ |
#define SPECIAL_NAMES { \ |
79 |
"sll", "special_01", "srl", "sra", "sllv", "special_05", "srlv", "srav", /* 0x00 - 0x07 */ \ |
"sll", "special_01", "srl", "sra", "sllv", "special_05", "srlv", "srav", /* 0x00 - 0x07 */ \ |
80 |
"jr", "jalr", "movz", "movn", "syscall", "break", "special_0e", "sync", /* 0x08 - 0x0f */ \ |
"jr", "jalr", "movz", "movn", "syscall","break", "special_0e", "sync", /* 0x08 - 0x0f */ \ |
81 |
"mfhi", "mthi", "mflo", "mtlo", "dsllv", "special_15", "dsrlv", "dsrav", /* 0x10 - 0x17 */ \ |
"mfhi", "mthi", "mflo", "mtlo", "dsllv", "special_15", "dsrlv", "dsrav", /* 0x10 - 0x17 */ \ |
82 |
"mult", "multu", "div", "divu", "dmult", "dmultu", "ddiv", "ddivu", /* 0x18 - 0x1f */ \ |
"mult", "multu", "div", "divu", "dmult", "dmultu", "ddiv", "ddivu", /* 0x18 - 0x1f */ \ |
83 |
"add", "addu", "sub", "subu", "and", "or", "xor", "nor", /* 0x20 - 0x27 */ \ |
"add", "addu", "sub", "subu", "and", "or", "xor", "nor", /* 0x20 - 0x27 */ \ |
84 |
"mfsa", "mtsa", "slt", "sltu", "special_2c", "daddu", "special_2e", "dsubu", /* 0x28 - 0x2f */ \ |
"special_28","special_29","slt", "sltu", "dadd", "daddu", "dsub", "dsubu", /* 0x28 - 0x2f */ \ |
85 |
"special_30", "special_31", "special_32", "special_33", "teq", "special_35", "special_36", "special_37", /* 0x30 - 0x37 */ \ |
"tge", "tgeu", "tlt", "tltu", "teq", "special_35", "tne", "special_37",/* 0x30 - 0x37 */ \ |
86 |
"dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32"/* 0x38 - 0x3f */ } |
"dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32" /* 0x38 - 0x3f */ } |
87 |
|
|
88 |
|
/* SPECIAL opcodes, when the rotate bit is set: */ |
89 |
|
#define SPECIAL_ROT_NAMES { \ |
90 |
|
"rot_00", "rot_01", "ror", "rot_03", "rot_04", "rot_05", "rorv", "rot_07", /* 0x00 - 0x07 */ \ |
91 |
|
"rot_08", "rot_09", "rot_0a", "rot_0b", "rot_0c", "rot_0d", "rot_0e", "rot_0f", /* 0x08 - 0x0f */ \ |
92 |
|
"rot_10", "rot_11", "rot_12", "rot_13", "rot_14", "rot_15", "drorv", "rot_17", /* 0x10 - 0x17 */ \ |
93 |
|
"rot_18", "rot_19", "rot_1a", "rot_1b", "rot_1c", "rot_1d", "rot_1e", "rot_1f", /* 0x18 - 0x1f */ \ |
94 |
|
"rot_20", "rot_21", "rot_22", "rot_23", "rot_24", "rot_25", "rot_26", "rot_27", /* 0x20 - 0x27 */ \ |
95 |
|
"rot_28", "rot_29", "rot_2a", "rot_2b", "rot_2c", "rot_2d", "rot_2e", "rot_2f", /* 0x28 - 0x2f */ \ |
96 |
|
"rot_30", "rot_31", "rot_32", "rot_33", "rot_34", "rot_35", "rot_36", "rot_37", /* 0x30 - 0x37 */ \ |
97 |
|
"rot_38", "rot_39", "dror", "rot_3b", "rot_3c", "rot_3d", "dror32", "rot_3f" /* 0x38 - 0x3f */ } |
98 |
|
|
99 |
#define SPECIAL2_NAMES { \ |
#define SPECIAL2_NAMES { \ |
100 |
"madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \ |
"madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \ |
101 |
"mov_xxx", "pmfhi_lo", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \ |
"special2_08", "special2_09", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \ |
102 |
"special2_10", "special2_11", "special2_12", "special2_13", "special2_14", "special2_15", "special2_16", "special2_17", /* 0x10 - 0x17 */ \ |
"special2_10", "special2_11", "special2_12", "special2_13", "special2_14", "special2_15", "special2_16", "special2_17", /* 0x10 - 0x17 */ \ |
103 |
"special2_18", "special2_19", "special2_1a", "special2_1b", "special2_1c", "special2_1d", "special2_1e", "special2_1f", /* 0x18 - 0x1f */ \ |
"special2_18", "special2_19", "special2_1a", "special2_1b", "special2_1c", "special2_1d", "special2_1e", "special2_1f", /* 0x18 - 0x1f */ \ |
104 |
"clz", "clo", "special2_22", "special2_23", "dclz", "dclo", "special2_26", "special2_27", /* 0x20 - 0x27 */ \ |
"clz", "clo", "special2_22", "special2_23", "dclz", "dclo", "special2_26", "special2_27", /* 0x20 - 0x27 */ \ |
105 |
"special2_28", "por", "special2_2a", "special2_2b", "special2_2c", "special2_2d", "special2_2e", "special2_2f", /* 0x28 - 0x2f */ \ |
"special2_28", "special2_29", "special2_2a", "special2_2b", "special2_2c", "special2_2d", "special2_2e", "special2_2f", /* 0x28 - 0x2f */ \ |
106 |
"special2_30", "special2_31", "special2_32", "special2_33", "special2_34", "special2_35", "special2_36", "special2_37", /* 0x30 - 0x37 */ \ |
"special2_30", "special2_31", "special2_32", "special2_33", "special2_34", "special2_35", "special2_36", "special2_37", /* 0x30 - 0x37 */ \ |
107 |
"special2_38", "special2_39", "special2_3a", "special2_3b", "special2_3c", "special2_3d", "special2_3e", "sdbbp" /* 0x38 - 0x3f */ } |
"special2_38", "special2_39", "special2_3a", "special2_3b", "special2_3c", "special2_3d", "special2_3e", "sdbbp" /* 0x38 - 0x3f */ } |
108 |
|
|
109 |
|
/* MMI (on R5900, TX79/C790) occupies the same space as SPECIAL2 */ |
110 |
|
#define MMI_NAMES { \ |
111 |
|
"madd", "maddu", "mmi_02", "mmi_03", "plzcw", "mmi_05", "mmi_06", "mmi_07", /* 0x00 - 0x07 */ \ |
112 |
|
"mmi0", "mmi2", "mmi_0a", "mmi_0b", "mmi_0c", "mmi_0d", "mmi_0e", "mmi_0f", /* 0x08 - 0x0f */ \ |
113 |
|
"mfhi1", "mthi1", "mflo1", "mtlo1", "mmi_14", "mmi_15", "mmi_16", "mmi_17", /* 0x10 - 0x17 */ \ |
114 |
|
"mult1", "multu1", "div1", "divu1", "mmi_1c", "mmi_1d", "mmi_1e", "mmi_1f", /* 0x18 - 0x1f */ \ |
115 |
|
"madd1", "maddu1", "mmi_22", "mmi_23", "mmi_24", "mmi_25", "mmi_26", "mmi_27", /* 0x20 - 0x27 */ \ |
116 |
|
"mmi1", "mmi3", "mmi_2a", "mmi_2b", "mmi_2c", "mmi_2d", "mmi_2e", "mmi_2f", /* 0x28 - 0x2f */ \ |
117 |
|
"pmfhl", "pmthl", "mmi_32", "mmi_33", "psllh", "mmi_35", "psrlh", "psrah", /* 0x30 - 0x37 */ \ |
118 |
|
"mmi_38", "mmi_39", "mmi_3a", "mmi_3b", "psllw", "mmi_3d", "psrlw", "psraw" /* 0x38 - 0x3f */ } |
119 |
|
|
120 |
|
#define MMI0_NAMES { \ |
121 |
|
"paddw", "psubw", "pcgtw", "pmaxw", /* 0x00 - 0x03 */ \ |
122 |
|
"paddh", "psubh", "pcgth", "pmaxh", /* 0x04 - 0x07 */ \ |
123 |
|
"paddb", "psubb", "pcgtb", "mmi0_0b", /* 0x08 - 0x0b */ \ |
124 |
|
"mmi0_0c", "mmi0_0d", "mmi0_0e", "mmi0_0f", /* 0x0c - 0x0f */ \ |
125 |
|
"paddsw", "psubsw", "pextlw", "ppacw", /* 0x10 - 0x13 */ \ |
126 |
|
"paddsh", "psubsh", "pextlh", "ppach", /* 0x14 - 0x17 */ \ |
127 |
|
"paddsb", "psubsb", "pextlb", "ppacb", /* 0x18 - 0x1b */ \ |
128 |
|
"mmi0_1c", "mmi0_1d", "pext5", "ppac5" /* 0x1c - 0x1f */ } |
129 |
|
|
130 |
|
#define MMI1_NAMES { \ |
131 |
|
"mmi1_00", "pabsw", "pceqw", "pminw", /* 0x00 - 0x03 */ \ |
132 |
|
"padsbh", "pabsh", "pceqh", "pminh", /* 0x04 - 0x07 */ \ |
133 |
|
"mmi1_08", "mmi1_09", "pceqb", "mmi1_0b", /* 0x08 - 0x0b */ \ |
134 |
|
"mmi1_0c", "mmi1_0d", "mmi1_0e", "mmi1_0f", /* 0x0c - 0x0f */ \ |
135 |
|
"padduw", "psubuw", "pextuw", "mmi1_13", /* 0x10 - 0x13 */ \ |
136 |
|
"padduh", "psubuh", "pextuh", "mmi1_17", /* 0x14 - 0x17 */ \ |
137 |
|
"paddub", "psubub", "pextub", "qfsrv", /* 0x18 - 0x1b */ \ |
138 |
|
"mmi1_1c", "mmi1_1d", "mmi1_1e", "mmi1_1f" /* 0x1c - 0x1f */ } |
139 |
|
|
140 |
|
#define MMI2_NAMES { \ |
141 |
|
"pmaddw", "mmi2_01", "psllvw", "psrlvw", /* 0x00 - 0x03 */ \ |
142 |
|
"pmsubw", "mmi2_05", "mmi2_06", "mmi2_07", /* 0x04 - 0x07 */ \ |
143 |
|
"pmfhi", "pmflo", "pinth", "mmi2_0b", /* 0x08 - 0x0b */ \ |
144 |
|
"pmultw", "pdivw", "pcpyld" , "mmi2_0f", /* 0x0c - 0x0f */ \ |
145 |
|
"pmaddh", "phmadh", "pand", "pxor", /* 0x10 - 0x13 */ \ |
146 |
|
"pmsubh", "phmsbh", "mmi2_16", "mmi2_17", /* 0x14 - 0x17 */ \ |
147 |
|
"mmi2_18", "mmi2_19", "pexeh", "prevh", /* 0x18 - 0x1b */ \ |
148 |
|
"pmulth", "pdivbw", "pexew", "prot3w" /* 0x1c - 0x1f */ } |
149 |
|
|
150 |
|
#define MMI3_NAMES { \ |
151 |
|
"pmadduw", "mmi3_01", "mmi3_02", "psravw", /* 0x00 - 0x03 */ \ |
152 |
|
"mmi3_04", "mmi3_05", "mmi3_06", "mmi3_07", /* 0x04 - 0x07 */ \ |
153 |
|
"pmthi", "pmtlo", "pinteh", "mmi3_0b", /* 0x08 - 0x0b */ \ |
154 |
|
"pmultuw", "pdivuw", "pcpyud" , "mmi3_0f", /* 0x0c - 0x0f */ \ |
155 |
|
"mmi3_10", "mmi3_11", "por", "pnor", /* 0x10 - 0x13 */ \ |
156 |
|
"mmi3_14", "mmi3_15", "mmi3_16", "mmi3_17", /* 0x14 - 0x17 */ \ |
157 |
|
"mmi3_18", "mmi3_19", "pexch", "pcpyh", /* 0x18 - 0x1b */ \ |
158 |
|
"mmi3_1c", "mmi3_1d", "pexcw", "mmi3_1f" /* 0x1c - 0x1f */ } |
159 |
|
|
160 |
|
#define SPECIAL3_NAMES { \ |
161 |
|
"ext", "dextm", "dextu", "dext", "ins", "dinsm", "dinsu", "dins", /* 0x00 - 0x07 */ \ |
162 |
|
"special3_08", "special3_09", "special3_0a", "special3_0b", "special3_0c", "special3_0d", "special3_0e", "special3_0f", /* 0x08 - 0x0f */ \ |
163 |
|
"special3_10", "special3_11", "special3_12", "special3_13", "special3_14", "special3_15", "special3_16", "special3_17", /* 0x10 - 0x17 */ \ |
164 |
|
"special3_18", "special3_19", "special3_1a", "special3_1b", "special3_1c", "special3_1d", "special3_1e", "special3_1f", /* 0x18 - 0x1f */ \ |
165 |
|
"bshfl", "special3_21", "special3_22", "special3_23", "dbshfl", "special3_25", "special3_26", "special3_27", /* 0x20 - 0x27 */ \ |
166 |
|
"special3_28", "special3_29", "special3_2a", "special3_2b", "special3_2c", "special3_2d", "special3_2e", "special3_2f", /* 0x28 - 0x2f */ \ |
167 |
|
"special3_30", "special3_31", "special3_32", "special3_33", "special3_34", "special3_35", "special3_36", "special3_37", /* 0x30 - 0x37 */ \ |
168 |
|
"special3_38", "special3_39", "special3_3a", "rdhwr", "special3_3c", "special3_3d", "special3_3e", "special3_3f" /* 0x38 - 0x3f */ } |
169 |
|
|
170 |
#define HI6_SPECIAL 0x00 /* 000000 */ |
#define HI6_SPECIAL 0x00 /* 000000 */ |
171 |
#define SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */ |
#define SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */ |
172 |
/* 0x01 000001 */ |
/* 0x01 000001 */ |
208 |
#define SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */ |
#define SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */ |
209 |
#define SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */ |
#define SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */ |
210 |
#define SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */ |
#define SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */ |
211 |
#define SPECIAL_MFSA 0x28 /* 101000 */ /* Undocumented R5900 ? */ |
#define SPECIAL_MFSA 0x28 /* 101000 */ /* R5900/TX79/C790 */ |
212 |
#define SPECIAL_MTSA 0x29 /* 101001 */ /* Undocumented R5900 ? */ |
#define SPECIAL_MTSA 0x29 /* 101001 */ /* R5900/TX79/C790 */ |
213 |
#define SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */ |
#define SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */ |
214 |
#define SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */ |
#define SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */ |
215 |
#define SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */ |
#define SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */ |
238 |
#define REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */ |
#define REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */ |
239 |
#define REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */ |
#define REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */ |
240 |
#define REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */ |
#define REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */ |
241 |
|
#define REGIMM_TGEI 0x08 /* 01000 */ |
242 |
|
#define REGIMM_TGEIU 0x09 /* 01001 */ |
243 |
|
#define REGIMM_TLTI 0x0a /* 01010 */ |
244 |
|
#define REGIMM_TLTIU 0x0b /* 01011 */ |
245 |
|
#define REGIMM_TEQI 0x0c /* 01100 */ |
246 |
|
#define REGIMM_TNEI 0x0e /* 01110 */ |
247 |
#define REGIMM_BLTZAL 0x10 /* 10000 */ |
#define REGIMM_BLTZAL 0x10 /* 10000 */ |
248 |
#define REGIMM_BGEZAL 0x11 /* 10001 */ |
#define REGIMM_BGEZAL 0x11 /* 10001 */ |
249 |
#define REGIMM_BLTZALL 0x12 /* 10010 */ |
#define REGIMM_BLTZALL 0x12 /* 10010 */ |
250 |
#define REGIMM_BGEZALL 0x13 /* 10011 */ |
#define REGIMM_BGEZALL 0x13 /* 10011 */ |
251 |
|
#define REGIMM_MTSAB 0x18 /* 11000 */ /* R5900/TX79/C790 */ |
252 |
|
#define REGIMM_MTSAH 0x19 /* 11001 */ /* R5900/TX79/C790 */ |
253 |
|
#define REGIMM_SYNCI 0x1f /* 11111 */ |
254 |
/* regimm ............... */ |
/* regimm ............... */ |
255 |
|
|
256 |
#define HI6_J 0x02 /* 000010 */ /* MIPS I */ |
#define HI6_J 0x02 /* 000010 */ /* MIPS I */ |
272 |
#define COPz_DMFCz 0x01 /* 00001 */ |
#define COPz_DMFCz 0x01 /* 00001 */ |
273 |
#define COPz_MTCz 0x04 /* 00100 */ |
#define COPz_MTCz 0x04 /* 00100 */ |
274 |
#define COPz_DMTCz 0x05 /* 00101 */ |
#define COPz_DMTCz 0x05 /* 00101 */ |
275 |
/* COP1 fmt codes = bits 25..21 (only if COP1): */ |
/* |
276 |
|
* For cop1 (the floating point coprocessor), if bits 25..21 are |
277 |
|
* a valid format, then bits 5..0 are the math opcode. |
278 |
|
* |
279 |
|
* Otherwise, bits 25..21 are the main coprocessor opcode. |
280 |
|
*/ |
281 |
#define COPz_CFCz 0x02 /* 00010 */ /* MIPS I */ |
#define COPz_CFCz 0x02 /* 00010 */ /* MIPS I */ |
282 |
#define COPz_CTCz 0x06 /* 00110 */ /* MIPS I */ |
#define COPz_CTCz 0x06 /* 00110 */ /* MIPS I */ |
283 |
/* COP0 opcodes = bits 4..0 (only if COP0 and CO=1): */ |
#define COPz_BCzc 0x08 /* 01000 */ |
284 |
#define COP0_TLBR 0x01 /* 00001 */ |
#define COPz_MFMCz 0x0b /* 01011 */ |
285 |
#define COP0_TLBWI 0x02 /* 00010 */ |
#define COP1_FMT_S 0x10 /* 10000 */ |
286 |
#define COP0_TLBWR 0x06 /* 00110 */ |
#define COP1_FMT_D 0x11 /* 10001 */ |
287 |
#define COP0_TLBP 0x08 /* 01000 */ |
#define COP1_FMT_W 0x14 /* 10100 */ |
288 |
#define COP0_RFE 0x10 /* 10000 */ |
#define COP1_FMT_L 0x15 /* 10101 */ |
289 |
#define COP0_ERET 0x18 /* 11000 */ |
#define COP1_FMT_PS 0x16 /* 10110 */ |
290 |
#define COP0_STANDBY 0x21 |
/* COP0 opcodes = bits 7..0 (only if COP0 and CO=1): */ |
291 |
#define COP0_SUSPEND 0x22 |
#define COP0_TLBR 0x01 /* 000001 */ |
292 |
#define COP0_HIBERNATE 0x23 |
#define COP0_TLBWI 0x02 /* 000010 */ |
293 |
|
#define COP0_TLBWR 0x06 /* 000110 */ |
294 |
|
#define COP0_TLBP 0x08 /* 001000 */ |
295 |
|
#define COP0_RFE 0x10 /* 010000 */ |
296 |
|
#define COP0_ERET 0x18 /* 011000 */ |
297 |
|
#define COP0_DERET 0x1f /* 011111 */ /* EJTAG */ |
298 |
|
#define COP0_WAIT 0x20 /* 100000 */ /* MIPS32/64 */ |
299 |
|
#define COP0_STANDBY 0x21 /* 100001 */ |
300 |
|
#define COP0_SUSPEND 0x22 /* 100010 */ |
301 |
|
#define COP0_HIBERNATE 0x23 /* 100011 */ |
302 |
|
#define COP0_EI 0x38 /* 111000 */ /* R5900/TX79/C790 */ |
303 |
|
#define COP0_DI 0x39 /* 111001 */ /* R5900/TX79/C790 */ |
304 |
#define HI6_COP1 0x11 /* 010001 */ |
#define HI6_COP1 0x11 /* 010001 */ |
305 |
#define HI6_COP2 0x12 /* 010010 */ |
#define HI6_COP2 0x12 /* 010010 */ |
306 |
#define HI6_COP3 0x13 /* 010011 */ |
#define HI6_COP3 0x13 /* 010011 */ |
318 |
#define SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */ |
#define SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */ |
319 |
#define SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */ |
#define SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */ |
320 |
#define SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */ |
#define SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */ |
|
#define SPECIAL2_MOV_XXX 0x08 /* 001000 */ /* Undocumented R5900 ? */ |
|
|
#define SPECIAL2_PMFHI 0x09 /* 001001 */ /* Undocumented R5900 ? */ |
|
321 |
#define SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */ |
#define SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */ |
322 |
#define SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */ |
#define SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */ |
323 |
#define SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */ |
#define SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */ |
324 |
#define SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */ |
#define SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */ |
|
#define SPECIAL2_POR 0x29 /* 101001 */ /* Undocumented R5900 ? */ |
|
325 |
#define SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */ |
#define SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */ |
326 |
|
/* MMI (R5900, TX79/C790) occupies the same opcode space as SPECIAL2: */ |
327 |
|
#define MMI_MADD 0x00 |
328 |
|
#define MMI_MADDU 0x01 |
329 |
|
#define MMI_PLZCW 0x04 |
330 |
|
#define MMI_MMI0 0x08 |
331 |
|
#define MMI0_PADDW 0x00 |
332 |
|
#define MMI0_PSUBW 0x01 |
333 |
|
#define MMI0_PCGTW 0x02 |
334 |
|
#define MMI0_PMAXW 0x03 |
335 |
|
#define MMI0_PADDH 0x04 |
336 |
|
#define MMI0_PSUBH 0x05 |
337 |
|
#define MMI0_PCGTH 0x06 |
338 |
|
#define MMI0_PMAXH 0x07 |
339 |
|
#define MMI0_PADDB 0x08 |
340 |
|
#define MMI0_PSUBB 0x09 |
341 |
|
#define MMI0_PCGTB 0x0a |
342 |
|
#define MMI0_PADDSW 0x10 |
343 |
|
#define MMI0_PSUBSW 0x11 |
344 |
|
#define MMI0_PEXTLW 0x12 |
345 |
|
#define MMI0_PPACW 0x13 |
346 |
|
#define MMI0_PADDSH 0x14 |
347 |
|
#define MMI0_PSUBSH 0x15 |
348 |
|
#define MMI0_PEXTLH 0x16 |
349 |
|
#define MMI0_PPACH 0x17 |
350 |
|
#define MMI0_PADDSB 0x18 |
351 |
|
#define MMI0_PSUBSB 0x19 |
352 |
|
#define MMI0_PEXTLB 0x1a |
353 |
|
#define MMI0_PPACB 0x1b |
354 |
|
#define MMI0_PEXT5 0x1e |
355 |
|
#define MMI0_PPAC5 0x1f |
356 |
|
#define MMI_MMI2 0x09 |
357 |
|
#define MMI2_PMADDW 0x00 |
358 |
|
#define MMI2_PSLLVW 0x02 |
359 |
|
#define MMI2_PSRLVW 0x03 |
360 |
|
#define MMI2_PMSUBW 0x04 |
361 |
|
#define MMI2_PMFHI 0x08 |
362 |
|
#define MMI2_PMFLO 0x09 |
363 |
|
#define MMI2_PINTH 0x0a |
364 |
|
#define MMI2_PMULTW 0x0c |
365 |
|
#define MMI2_PDIVW 0x0d |
366 |
|
#define MMI2_PCPYLD 0x0e |
367 |
|
#define MMI2_PMADDH 0x10 |
368 |
|
#define MMI2_PHMADH 0x11 |
369 |
|
#define MMI2_PAND 0x12 |
370 |
|
#define MMI2_PXOR 0x13 |
371 |
|
#define MMI2_PMSUBH 0x14 |
372 |
|
#define MMI2_PHMSBH 0x15 |
373 |
|
#define MMI2_PEXEH 0x1a |
374 |
|
#define MMI2_PREVH 0x1b |
375 |
|
#define MMI2_PMULTH 0x1c |
376 |
|
#define MMI2_PDIVBW 0x1d |
377 |
|
#define MMI2_PEXEW 0x1e |
378 |
|
#define MMI2_PROT3W 0x1f |
379 |
|
#define MMI_MFHI1 0x10 |
380 |
|
#define MMI_MTHI1 0x11 |
381 |
|
#define MMI_MFLO1 0x12 |
382 |
|
#define MMI_MTLO1 0x13 |
383 |
|
#define MMI_MULT1 0x18 |
384 |
|
#define MMI_MULTU1 0x19 |
385 |
|
#define MMI_DIV1 0x1a |
386 |
|
#define MMI_DIVU1 0x1b |
387 |
|
#define MMI_MADD1 0x20 |
388 |
|
#define MMI_MADDU1 0x21 |
389 |
|
#define MMI_MMI1 0x28 |
390 |
|
#define MMI1_PABSW 0x01 |
391 |
|
#define MMI1_PCEQW 0x02 |
392 |
|
#define MMI1_PMINW 0x03 |
393 |
|
#define MMI1_PADSBH 0x04 |
394 |
|
#define MMI1_PABSH 0x05 |
395 |
|
#define MMI1_PCEQH 0x06 |
396 |
|
#define MMI1_PMINH 0x07 |
397 |
|
#define MMI1_PCEQB 0x0a |
398 |
|
#define MMI1_PADDUW 0x10 |
399 |
|
#define MMI1_PSUBUW 0x11 |
400 |
|
#define MMI1_PEXTUW 0x12 |
401 |
|
#define MMI1_PADDUH 0x14 |
402 |
|
#define MMI1_PSUBUH 0x15 |
403 |
|
#define MMI1_PEXTUH 0x16 |
404 |
|
#define MMI1_PADDUB 0x18 |
405 |
|
#define MMI1_PSUBUB 0x19 |
406 |
|
#define MMI1_PEXTUB 0x1a |
407 |
|
#define MMI1_QFSRV 0x1b |
408 |
|
#define MMI_MMI3 0x29 |
409 |
|
#define MMI3_PMADDUW 0x00 |
410 |
|
#define MMI3_PSRAVW 0x03 |
411 |
|
#define MMI3_PMTHI 0x08 |
412 |
|
#define MMI3_PMTLO 0x09 |
413 |
|
#define MMI3_PINTEH 0x0a |
414 |
|
#define MMI3_PMULTUW 0x0c |
415 |
|
#define MMI3_PDIVUW 0x0d |
416 |
|
#define MMI3_PCPYUD 0x0e |
417 |
|
#define MMI3_POR 0x12 |
418 |
|
#define MMI3_PNOR 0x13 |
419 |
|
#define MMI3_PEXCH 0x1a |
420 |
|
#define MMI3_PCPYH 0x1b |
421 |
|
#define MMI3_PEXCW 0x1e |
422 |
|
#define MMI_PMFHL 0x30 |
423 |
|
#define MMI_PMTHL 0x31 |
424 |
|
#define MMI_PSLLH 0x34 |
425 |
|
#define MMI_PSRLH 0x36 |
426 |
|
#define MMI_PSRAH 0x37 |
427 |
|
#define MMI_PSLLW 0x3c |
428 |
|
#define MMI_PSRLW 0x3e |
429 |
|
#define MMI_PSRAW 0x3f |
430 |
/* JALX (TODO) 0x1d 011101 */ |
/* JALX (TODO) 0x1d 011101 */ |
431 |
#define HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */ |
#define HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */ |
432 |
#define HI6_SQ 0x1f /* 011111 */ /* R5900 ? */ |
/* TODO: MDMX opcodes */ |
433 |
|
#define HI6_SQ_SPECIAL3 0x1f /* 011111 */ /* sq on R5900, SPECIAL3 on MIPS32/64 rev 2 */ |
434 |
|
#define SPECIAL3_EXT 0x00 /* 000000 */ |
435 |
|
#define SPECIAL3_DEXTM 0x01 /* 000001 */ |
436 |
|
#define SPECIAL3_DEXTU 0x02 /* 000010 */ |
437 |
|
#define SPECIAL3_DEXT 0x03 /* 000011 */ |
438 |
|
#define SPECIAL3_INS 0x04 /* 000100 */ |
439 |
|
#define SPECIAL3_DINSM 0x05 /* 000101 */ |
440 |
|
#define SPECIAL3_DINSU 0x06 /* 000110 */ |
441 |
|
#define SPECIAL3_DINS 0x07 /* 000111 */ |
442 |
|
#define SPECIAL3_BSHFL 0x20 /* 100000 */ |
443 |
|
#define BSHFL_WSBH 0x002 /* 00000..00010 */ |
444 |
|
#define BSHFL_SEB 0x010 /* 00000..10000 */ |
445 |
|
#define BSHFL_SEH 0x018 /* 00000..11000 */ |
446 |
|
#define SPECIAL3_DBSHFL 0x24 /* 100100 */ |
447 |
|
#define BSHFL_DSBH 0x002 /* 00000..00010 */ |
448 |
|
#define BSHFL_DSHD 0x005 /* 00000..00101 */ |
449 |
|
#define SPECIAL3_RDHWR 0x3b /* 111011 */ |
450 |
#define HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
#define HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
451 |
#define HI6_LH 0x21 /* 100001 */ /* MIPS I */ |
#define HI6_LH 0x21 /* 100001 */ /* MIPS I */ |
452 |
#define HI6_LWL 0x22 /* 100010 */ /* MIPS I */ |
#define HI6_LWL 0x22 /* 100010 */ /* MIPS I */ |
481 |
#define HI6_SD 0x3f /* 111111 */ /* MIPS III */ |
#define HI6_SD 0x3f /* 111111 */ /* MIPS III */ |
482 |
|
|
483 |
|
|
484 |
#endif /* OPCODES_H */ |
#endif /* OPCODES_MIPS_H */ |
|
|
|