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#define OPCODES_MIPS_H |
#define OPCODES_MIPS_H |
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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: opcodes_mips.h,v 1.14 2006/08/11 17:43:30 debug Exp $ |
* $Id: opcodes_mips.h,v 1.16 2006/12/30 13:31:01 debug Exp $ |
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* |
* |
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* MIPS opcodes, gathered from various sources. |
* MIPS opcodes, gathered from various sources. |
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* |
* |
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"tge", "tgeu", "tlt", "tltu", "teq", "special_35", "tne", "special_37",/* 0x30 - 0x37 */ \ |
"tge", "tgeu", "tlt", "tltu", "teq", "special_35", "tne", "special_37",/* 0x30 - 0x37 */ \ |
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"dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32" /* 0x38 - 0x3f */ } |
"dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32" /* 0x38 - 0x3f */ } |
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/* SPECIAL opcodes, when the rotate bit is set: */ |
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#define SPECIAL_ROT_NAMES { \ |
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"rot_00", "rot_01", "ror", "rot_03", "rot_04", "rot_05", "rorv", "rot_07", /* 0x00 - 0x07 */ \ |
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"rot_08", "rot_09", "rot_0a", "rot_0b", "rot_0c", "rot_0d", "rot_0e", "rot_0f", /* 0x08 - 0x0f */ \ |
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"rot_10", "rot_11", "rot_12", "rot_13", "rot_14", "rot_15", "drorv", "rot_17", /* 0x10 - 0x17 */ \ |
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"rot_18", "rot_19", "rot_1a", "rot_1b", "rot_1c", "rot_1d", "rot_1e", "rot_1f", /* 0x18 - 0x1f */ \ |
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"rot_20", "rot_21", "rot_22", "rot_23", "rot_24", "rot_25", "rot_26", "rot_27", /* 0x20 - 0x27 */ \ |
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"rot_28", "rot_29", "rot_2a", "rot_2b", "rot_2c", "rot_2d", "rot_2e", "rot_2f", /* 0x28 - 0x2f */ \ |
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"rot_30", "rot_31", "rot_32", "rot_33", "rot_34", "rot_35", "rot_36", "rot_37", /* 0x30 - 0x37 */ \ |
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"rot_38", "rot_39", "dror", "rot_3b", "rot_3c", "rot_3d", "dror32", "rot_3f" /* 0x38 - 0x3f */ } |
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#define SPECIAL2_NAMES { \ |
#define SPECIAL2_NAMES { \ |
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"madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \ |
"madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \ |
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"special2_08", "special2_09", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \ |
"special2_08", "special2_09", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \ |
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#define SPECIAL3_DINSU 0x06 /* 000110 */ |
#define SPECIAL3_DINSU 0x06 /* 000110 */ |
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#define SPECIAL3_DINS 0x07 /* 000111 */ |
#define SPECIAL3_DINS 0x07 /* 000111 */ |
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#define SPECIAL3_BSHFL 0x20 /* 100000 */ |
#define SPECIAL3_BSHFL 0x20 /* 100000 */ |
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#define BSHFL_WSBH 0x02 /* 00010 */ |
#define BSHFL_WSBH 0x002 /* 00000..00010 */ |
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#define BSHFL_SEB 0x010 /* 00000..10000 */ |
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#define BSHFL_SEH 0x018 /* 00000..11000 */ |
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#define SPECIAL3_DBSHFL 0x24 /* 100100 */ |
#define SPECIAL3_DBSHFL 0x24 /* 100100 */ |
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#define BSHFL_DSBH 0x002 /* 00000..00010 */ |
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#define BSHFL_DSHD 0x005 /* 00000..00101 */ |
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#define SPECIAL3_RDHWR 0x3b /* 111011 */ |
#define SPECIAL3_RDHWR 0x3b /* 111011 */ |
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#define HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
#define HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
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#define HI6_LH 0x21 /* 100001 */ /* MIPS I */ |
#define HI6_LH 0x21 /* 100001 */ /* MIPS I */ |