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/* gxemul: $Id: ohcireg.h,v 1.1 2005/04/10 21:18:24 debug Exp $ */ |
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/* $NetBSD: ohcireg.h,v 1.19 2002/07/11 21:14:27 augustss Exp $ */ |
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/* $FreeBSD: src/sys/dev/usb/ohcireg.h,v 1.8 1999/11/17 22:33:40 n_hibma Exp $ */ |
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|
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#ifndef OHCIREG_H |
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#define OHCIREG_H |
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|
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/* |
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* Copyright (c) 1998 The NetBSD Foundation, Inc. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to The NetBSD Foundation |
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* by Lennart Augustsson (lennart@augustsson.net) at |
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* Carlstedt Research & Technology. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the NetBSD |
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* Foundation, Inc. and its contributors. |
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* 4. Neither the name of The NetBSD Foundation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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/*** PCI config registers ***/ |
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|
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#define PCI_CBMEM 0x10 /* configuration base memory */ |
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|
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#define PCI_INTERFACE_OHCI 0x10 |
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|
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/*** OHCI registers */ |
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|
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#define OHCI_REVISION 0x00 /* OHCI revision # */ |
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#define OHCI_REV_LO(rev) ((rev)&0xf) |
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#define OHCI_REV_HI(rev) (((rev)>>4)&0xf) |
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#define OHCI_REV_LEGACY(rev) ((rev) & 0x100) |
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|
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#define OHCI_CONTROL 0x04 |
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#define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */ |
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#define OHCI_RATIO_1_1 0x00000000 |
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#define OHCI_RATIO_1_2 0x00000001 |
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#define OHCI_RATIO_1_3 0x00000002 |
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#define OHCI_RATIO_1_4 0x00000003 |
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#define OHCI_PLE 0x00000004 /* Periodic List Enable */ |
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#define OHCI_IE 0x00000008 /* Isochronous Enable */ |
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#define OHCI_CLE 0x00000010 /* Control List Enable */ |
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#define OHCI_BLE 0x00000020 /* Bulk List Enable */ |
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#define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalState */ |
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#define OHCI_HCFS_RESET 0x00000000 |
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#define OHCI_HCFS_RESUME 0x00000040 |
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#define OHCI_HCFS_OPERATIONAL 0x00000080 |
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#define OHCI_HCFS_SUSPEND 0x000000c0 |
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#define OHCI_IR 0x00000100 /* Interrupt Routing */ |
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#define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */ |
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#define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */ |
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#define OHCI_COMMAND_STATUS 0x08 |
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#define OHCI_HCR 0x00000001 /* Host Controller Reset */ |
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#define OHCI_CLF 0x00000002 /* Control List Filled */ |
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#define OHCI_BLF 0x00000004 /* Bulk List Filled */ |
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#define OHCI_OCR 0x00000008 /* Ownership Change Request */ |
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#define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */ |
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#define OHCI_INTERRUPT_STATUS 0x0c |
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#define OHCI_SO 0x00000001 /* Scheduling Overrun */ |
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#define OHCI_WDH 0x00000002 /* Writeback Done Head */ |
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#define OHCI_SF 0x00000004 /* Start of Frame */ |
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#define OHCI_RD 0x00000008 /* Resume Detected */ |
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#define OHCI_UE 0x00000010 /* Unrecoverable Error */ |
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#define OHCI_FNO 0x00000020 /* Frame Number Overflow */ |
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#define OHCI_RHSC 0x00000040 /* Root Hub Status Change */ |
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#define OHCI_OC 0x40000000 /* Ownership Change */ |
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#define OHCI_MIE 0x80000000 /* Master Interrupt Enable */ |
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#define OHCI_INTERRUPT_ENABLE 0x10 |
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#define OHCI_INTERRUPT_DISABLE 0x14 |
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#define OHCI_HCCA 0x18 |
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#define OHCI_PERIOD_CURRENT_ED 0x1c |
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#define OHCI_CONTROL_HEAD_ED 0x20 |
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#define OHCI_CONTROL_CURRENT_ED 0x24 |
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#define OHCI_BULK_HEAD_ED 0x28 |
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#define OHCI_BULK_CURRENT_ED 0x2c |
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#define OHCI_DONE_HEAD 0x30 |
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#define OHCI_FM_INTERVAL 0x34 |
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#define OHCI_GET_IVAL(s) ((s) & 0x3fff) |
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#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) |
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#define OHCI_FIT 0x80000000 |
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#define OHCI_FM_REMAINING 0x38 |
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#define OHCI_FM_NUMBER 0x3c |
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#define OHCI_PERIODIC_START 0x40 |
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#define OHCI_LS_THRESHOLD 0x44 |
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#define OHCI_RH_DESCRIPTOR_A 0x48 |
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#define OHCI_GET_NDP(s) ((s) & 0xff) |
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#define OHCI_PSM 0x0100 /* Power Switching Mode */ |
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#define OHCI_NPS 0x0200 /* No Power Switching */ |
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#define OHCI_DT 0x0400 /* Device Type */ |
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#define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */ |
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#define OHCI_NOCP 0x1000 /* No Overcurrent Protection */ |
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#define OHCI_GET_POTPGT(s) ((s) >> 24) |
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#define OHCI_RH_DESCRIPTOR_B 0x4c |
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#define OHCI_RH_STATUS 0x50 |
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#define OHCI_LPS 0x00000001 /* Local Power Status */ |
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#define OHCI_OCI 0x00000002 /* OverCurrent Indicator */ |
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#define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */ |
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#define OHCI_LPSC 0x00010000 /* Local Power Status Change */ |
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#define OHCI_CCIC 0x00020000 /* OverCurrent Indicator Change */ |
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#define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */ |
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#define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */ |
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|
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#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) |
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#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \ |
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OHCI_FNO | OHCI_RHSC | OHCI_OC) |
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#define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) |
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|
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#define OHCI_FSMPS(i) (((i-210)*6/7) << 16) |
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#define OHCI_PERIODIC(i) ((i)*9/10) |
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|
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typedef u_int32_t ohci_physaddr_t; |
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|
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#define OHCI_NO_INTRS 32 |
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struct ohci_hcca { |
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ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS]; |
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u_int32_t hcca_frame_number; |
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ohci_physaddr_t hcca_done_head; |
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#define OHCI_DONE_INTRS 1 |
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}; |
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#define OHCI_HCCA_SIZE 256 |
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#define OHCI_HCCA_ALIGN 256 |
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|
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#define OHCI_PAGE_SIZE 0x1000 |
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#define OHCI_PAGE(x) ((x) &~ 0xfff) |
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#define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) |
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|
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typedef struct { |
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u_int32_t ed_flags; |
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#define OHCI_ED_GET_FA(s) ((s) & 0x7f) |
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#define OHCI_ED_ADDRMASK 0x0000007f |
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#define OHCI_ED_SET_FA(s) (s) |
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#define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf) |
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#define OHCI_ED_SET_EN(s) ((s) << 7) |
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#define OHCI_ED_DIR_MASK 0x00001800 |
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#define OHCI_ED_DIR_TD 0x00000000 |
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#define OHCI_ED_DIR_OUT 0x00000800 |
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#define OHCI_ED_DIR_IN 0x00001000 |
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#define OHCI_ED_SPEED 0x00002000 |
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#define OHCI_ED_SKIP 0x00004000 |
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#define OHCI_ED_FORMAT_GEN 0x00000000 |
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#define OHCI_ED_FORMAT_ISO 0x00008000 |
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#define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff) |
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#define OHCI_ED_SET_MAXP(s) ((s) << 16) |
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#define OHCI_ED_MAXPMASK (0x7ff << 16) |
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ohci_physaddr_t ed_tailp; |
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ohci_physaddr_t ed_headp; |
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#define OHCI_HALTED 0x00000001 |
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#define OHCI_TOGGLECARRY 0x00000002 |
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#define OHCI_HEADMASK 0xfffffffc |
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ohci_physaddr_t ed_nexted; |
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} ohci_ed_t; |
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/* #define OHCI_ED_SIZE 16 */ |
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#define OHCI_ED_ALIGN 16 |
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|
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typedef struct { |
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u_int32_t td_flags; |
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#define OHCI_TD_R 0x00040000 /* Buffer Rounding */ |
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#define OHCI_TD_DP_MASK 0x00180000 /* Direction / PID */ |
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#define OHCI_TD_SETUP 0x00000000 |
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#define OHCI_TD_OUT 0x00080000 |
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#define OHCI_TD_IN 0x00100000 |
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#define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */ |
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#define OHCI_TD_SET_DI(x) ((x) << 21) |
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#define OHCI_TD_NOINTR 0x00e00000 |
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#define OHCI_TD_INTR_MASK 0x00e00000 |
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#define OHCI_TD_TOGGLE_CARRY 0x00000000 |
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#define OHCI_TD_TOGGLE_0 0x02000000 |
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#define OHCI_TD_TOGGLE_1 0x03000000 |
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#define OHCI_TD_TOGGLE_MASK 0x03000000 |
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#define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) /* Error Count */ |
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#define OHCI_TD_GET_CC(x) ((x) >> 28) /* Condition Code */ |
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#define OHCI_TD_NOCC 0xf0000000 |
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ohci_physaddr_t td_cbp; /* Current Buffer Pointer */ |
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ohci_physaddr_t td_nexttd; /* Next TD */ |
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ohci_physaddr_t td_be; /* Buffer End */ |
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} ohci_td_t; |
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/* #define OHCI_TD_SIZE 16 */ |
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#define OHCI_TD_ALIGN 16 |
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|
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#define OHCI_ITD_NOFFSET 8 |
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typedef struct { |
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u_int32_t itd_flags; |
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#define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff) |
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#define OHCI_ITD_SET_SF(x) ((x) & 0xffff) |
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#define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */ |
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#define OHCI_ITD_SET_DI(x) ((x) << 21) |
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#define OHCI_ITD_NOINTR 0x00e00000 |
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#define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) /* Frame Count */ |
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#define OHCI_ITD_SET_FC(x) (((x)-1) << 24) |
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#define OHCI_ITD_GET_CC(x) ((x) >> 28) /* Condition Code */ |
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#define OHCI_ITD_NOCC 0xf0000000 |
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ohci_physaddr_t itd_bp0; /* Buffer Page 0 */ |
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ohci_physaddr_t itd_nextitd; /* Next ITD */ |
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ohci_physaddr_t itd_be; /* Buffer End */ |
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u_int16_t itd_offset[OHCI_ITD_NOFFSET]; /* Buffer offsets */ |
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#define itd_pswn itd_offset /* Packet Status Word*/ |
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#define OHCI_ITD_PAGE_SELECT 0x00001000 |
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#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) |
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#define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */ |
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#define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */ |
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} ohci_itd_t; |
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/* #define OHCI_ITD_SIZE 32 */ |
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#define OHCI_ITD_ALIGN 32 |
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|
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|
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#define OHCI_CC_NO_ERROR 0 |
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#define OHCI_CC_CRC 1 |
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#define OHCI_CC_BIT_STUFFING 2 |
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#define OHCI_CC_DATA_TOGGLE_MISMATCH 3 |
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#define OHCI_CC_STALL 4 |
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#define OHCI_CC_DEVICE_NOT_RESPONDING 5 |
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#define OHCI_CC_PID_CHECK_FAILURE 6 |
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#define OHCI_CC_UNEXPECTED_PID 7 |
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#define OHCI_CC_DATA_OVERRUN 8 |
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#define OHCI_CC_DATA_UNDERRUN 9 |
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#define OHCI_CC_BUFFER_OVERRUN 12 |
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#define OHCI_CC_BUFFER_UNDERRUN 13 |
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#define OHCI_CC_NOT_ACCESSED 15 |
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|
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/* Some delay needed when changing certain registers. */ |
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#define OHCI_ENABLE_POWER_DELAY 5 |
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#define OHCI_READ_DESC_DELAY 5 |
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|
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#endif /* OHCIREG_H */ |
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