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Revision Log
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501 Continuing a little on m88k disassembly (control registers,
more instructions).
Adding a dummy mvme88k machine mode.
20070502 Re-adding MIPS load/store alignment exceptions.
20070503 Implementing more of the M88K disassembly code.
20070504 Adding disassembly of some more M88K load/store instructions.
Implementing some relatively simple M88K instructions (br.n,
xor[.u] imm, and[.u] imm).
20070505 Implementing M88K three-register and, or, xor, and jmp[.n],
bsr[.n] including function call trace stuff.
Applying a patch from Bruce M. Simpson which implements the
SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
the yamon PROM emulation.
20070506 Implementing M88K bb0[.n] and bb1[.n], and skeletons for
ldcr and stcr (although no control regs are implemented yet).
20070509 Found and fixed the bug which caused Linux for QEMU_MIPS to
stop working in 0.4.5.1: It was a faulty change to the MIPS
'sc' and 'scd' instructions I made while going through gcc -W
warnings on 20070428.
20070510 Updating the Linux/QEMU_MIPS section in guestoses.html to
use mips-test-0.2.tar.gz instead of 0.1.
A big thank you to Miod Vallat for sending me M88K manuals.
Implementing more M88K instructions (addu, subu, div[u], mulu,
ext[u], clr, set, cmp).
20070511 Fixing bugs in the M88K "and" and "and.u" instructions (found
by comparing against the manual).
Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
generated)) and some more control register details.
Cleanup: Removing the experimental AVR emulation mode and
corresponding devices; AVR emulation wasn't really meaningful.
Implementing autogeneration of most M88K loads/stores. The
rectangle drawing demo (with -O0) for M88K runs :-)
Beginning on M88K exception handling.
More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
Adding some skeleton MVME PROM ("BUG") emulation.
20070512 Fixing a bug in the M88K cmp instruction.
Adding the M88K lda (scaled register) instruction.
Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
Removing the unused tick_hz stuff from the machine struct.
Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
far enough to display the Copyright banner :-)
Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
Adding a dev_mvme187, for MVME187-specific devices/registers.
OpenBSD/mvme88k prints more boot messages. :)
20070515 Continuing on MVME187 emulation (adding more devices, beginning
on the CMMUs, etc).
Adding the M88K and.c, xor.c, and or.c instructions, and making
sure that mul, div, etc cause exceptions if executed when SFD1
is disabled.
20070517 Continuing on M88K and MVME187 emulation in general; moving
the CMMU registers to the CPU struct, separating dev_pcc2 from
dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
Implementing the clock part of dev_mk48txx.
Implementing the M88K fstcr and xcr instructions.
Implementing m88k_cpu_tlbdump().
Beginning on the implementation of a separate address space
for M88K .usr loads/stores.
20070520 Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
Dnard, and Zaurus machine modes.
Experimenting with dyntrans to_be_translated read-ahead. It
seems to give a very small performance increase for MIPS
emulation, but a large performance degradation for SuperH. Hm.
20070522 Disabling correct SuperH ITLB emulation; it does not seem to be
necessary in order to let SH4 guest OSes run, and it slows down
userspace code.
Implementing "samepage" branches for SuperH emulation, and some
other minor speed hacks.
20070525 Continuing on M88K memory-related stuff: exceptions, memory
transaction register contents, etc.
Implementing the M88K subu.ci instruction.
Removing the non-working (skeleton) Iyonix machine mode.
OpenBSD/mvme88k reaches userland :-), starts executing
/sbin/init's instructions, and issues a few syscalls, before
crashing.
20070526 Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
the correct time-of-day.
Implementing a generic IRQ controller for the test machines
(dev_irqc), similar to a proposed patch from Petr Stepan.
Experimenting some more with translation read-ahead.
Adding an "expect" script for automated OpenBSD/landisk
install regression/performance tests.
20070527 Adding a dummy mmEye (SH3) machine mode skeleton.
FINALLY found the strange M88K bug I have been hunting: I had
not emulated the SNIP value for exceptions occurring in
branch delay slots correctly.
Implementing correct exceptions for 64-bit M88K loads/stores.
Address to symbol lookups are now disabled when M88K is
running in usermode (because usermode addresses don't have
anything to do with supervisor addresses).
20070531 Removing the mmEye machine mode skeleton.
20070604 Some minor code cleanup.
20070605 Moving src/useremul.c into a subdir (src/useremul/), and
cleaning up some more legacy constructs.
Adding -Wstrict-aliasing and -fstrict-aliasing detection to
the configure script.
20070606 Adding a check for broken GCC on Solaris to the configure
script. (GCC 3.4.3 on Solaris cannot handle static variables
which are initialized to 0 or NULL. :-/)
Removing the old (non-working) ARC emulation modes: NEC RD94,
R94, R96, and R98, and the last traces of Olivetti M700 and
Deskstation Tyne.
Removing the non-working skeleton WDSC device (dev_wdsc).
20070607 Thinking about how to use the host's cc + ld at runtime to
generate native code. (See experiments/native_cc_ld_test.i
for an example.)
20070608 Adding a program counter sampling timer, which could be useful
for native code generation experiments.
The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
should always be set, to allow a 5000/200 PROM to boot.
20070609 Moving out breakpoint details from the machine struct into
a helper struct, and removing the limit on max nr of
breakpoints.
20070610 Moving out tick functions into a helper struct as well (which
also gets rid of the max limit).
20070612 FINALLY figured out why Debian/DECstation stopped working when
translation read-ahead was enabled: in src/memory_rw.c, the
call to invalidate_code_translation was made also if the
memory access was an instruction load (if the page was mapped
as writable); it shouldn't be called in that case.
20070613 Implementing some more MIPS32/64 revision 2 instructions: di,
ei, ext, dext, dextm, dextu, and ins.
20070614 Implementing an instruction combination for the NetBSD/arm
idle loop (making the host not use any cpu if NetBSD/arm
inside the emulator is not using any cpu).
Increasing the nr of ARM VPH entries from 128 to 384.
20070615 Removing the ENABLE_arch stuff from the configure script, so
that all included architectures are included in both release
and development builds.
Moving memory related helper functions from misc.c to memory.c.
Adding preliminary instructions for netbooting NetBSD/pmppc to
guestoses.html; it doesn't work yet, there are weird timeouts.
Beginning a total rewrite of the userland emulation modes
(removing all emulation modes, beginning from scratch with
NetBSD/MIPS and FreeBSD/Alpha only).
20070616 After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
only cleared for the last segment when transmitting, not all
segments), NetBSD/pmppc boots with root-on-nfs without the
timeouts. Updating guestoses.html.
Removing the skeleton PSP (Playstation Portable) mode.
Moving X11-related stuff in the machine struct into a helper
struct.
Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
macro (which prints a meaningful error message).
Adding a COMMENT to each machine and device (for automagic
.index comment generation).
Doing regression testing for the next release.
============== RELEASE 0.4.6 ==============
| 1 | /* GXemul: $Id: mvme_pcctworeg.h,v 1.1 2007/05/15 12:35:14 debug Exp $ */ |
| 2 | /* $OpenBSD: pcctworeg.h,v 1.8 2006/04/27 20:19:28 miod Exp $ */ |
| 3 | |
| 4 | #ifndef MVME_PCCTWOREG_H |
| 5 | #define MVME_PCCTWOREG_H |
| 6 | |
| 7 | /* |
| 8 | * Memory map for PCC2 chip found in MVME1x7 boards. |
| 9 | * |
| 10 | * PCCchip2 control and status register can be accessed as bytes (8 bits), |
| 11 | * two-bytes (16 bits), or four-bytes (32 bits). |
| 12 | */ |
| 13 | |
| 14 | #define PCC2_BASE 0xfff42000 |
| 15 | #define PCC2_SIZE 0x0040 |
| 16 | |
| 17 | #define PCCTWO_CHIPID 0x0000 |
| 18 | #define PCCTWO_CHIPREV 0x0001 |
| 19 | #define PCCTWO_GENCTL 0x0002 |
| 20 | #define PCCTWO_VECBASE 0x0003 |
| 21 | #define PCCTWO_T1CMP 0x0004 |
| 22 | #define PCCTWO_T1COUNT 0x0008 |
| 23 | #define PCCTWO_T2CMP 0x000c |
| 24 | #define PCCTWO_T2COUNT 0x0010 |
| 25 | #define PCCTWO_PSCALECNT 0x0014 |
| 26 | #define PCCTWO_PSCALEADJ 0x0015 |
| 27 | #define PCCTWO_T2CTL 0x0016 |
| 28 | #define PCCTWO_T1CTL 0x0017 |
| 29 | #define PCCTWO_GPIO_ICR 0x0018 |
| 30 | #define PCCTWO_GPIO_PCR 0x0019 |
| 31 | #define PCCTWO_T2ICR 0x001a |
| 32 | #define PCCTWO_T1ICR 0x001b |
| 33 | #define PCCTWO_SCCERR 0x001c |
| 34 | #define PCCTWO_SCCICR 0x001d |
| 35 | #define PCCTWO_SCCTX 0x001e |
| 36 | #define PCCTWO_SCCRX 0x001f |
| 37 | #define PCCTWO_SCCMOIACK 0x0023 |
| 38 | #define PCCTWO_SCCTXIACK 0x0025 |
| 39 | #define PCCTWO_SCCRXIACK 0x0027 |
| 40 | #define PCCTWO_IEERR 0x0028 |
| 41 | #define PCCTWO_IEICR 0x002a |
| 42 | #define PCCTWO_IEBERR 0x002b |
| 43 | #define PCCTWO_SCSIERR 0x002c |
| 44 | #define PCCTWO_SCSIICR 0x002f |
| 45 | #define PCCTWO_PRTICR 0x0030 |
| 46 | #define PCCTWO_PTRFICR 0x0031 |
| 47 | #define PCCTWO_PTRSICR 0x0032 |
| 48 | #define PCCTWO_PTRPICR 0x0033 |
| 49 | #define PCCTWO_PRTBICR 0x0034 |
| 50 | #define PCCTWO_PRTSTATUS 0x0036 |
| 51 | #define PCCTWO_PRTCTL 0x0037 |
| 52 | #define PCCTWO_SPEED 0x0038 |
| 53 | #define PCCTWO_PRTDATA 0x003a |
| 54 | /* The following registers are not valid on MVME197 */ |
| 55 | #define PCCTWO_IPL 0x003e |
| 56 | #define PCCTWO_MASK 0x003f |
| 57 | |
| 58 | #define PCC2_ID 0x20 /* value at CHIPID */ |
| 59 | |
| 60 | /* General Control Register */ |
| 61 | #define PCC2_DR0 0x80 |
| 62 | #define PCC2_C040 0x04 |
| 63 | #define PCC2_MIEN 0x02 |
| 64 | #define PCC2_FAST 0x01 |
| 65 | |
| 66 | /* Top 4 bits of the PCC2 VBR. Will be the top 4 bits of the vector */ |
| 67 | #define PCC2_VECT 0x50 |
| 68 | |
| 69 | /* Bottom 4 bits of the vector returned during IACK cycle */ |
| 70 | #define PCC2V_PPBUSY 0x00 /* lowest */ |
| 71 | #define PCC2V_PPPE 0x01 |
| 72 | #define PCC2V_PPSELECT 0x02 |
| 73 | #define PCC2V_PPFAULT 0x03 |
| 74 | #define PCC2V_PPACK 0x04 |
| 75 | #define PCC2V_SCSI 0x05 |
| 76 | #define PCC2V_IEFAIL 0x06 |
| 77 | #define PCC2V_IE 0x07 |
| 78 | #define PCC2V_TIMER2 0x08 |
| 79 | #define PCC2V_TIMER1 0x09 |
| 80 | #define PCC2V_GPIO 0x0a |
| 81 | #define PCC2V_SCC_RXE 0x0c |
| 82 | #define PCC2V_SCC_M (PCC2V_SCC_RXE + 1) |
| 83 | #define PCC2V_SCC_TX (PCC2V_SCC_M + 1) |
| 84 | #define PCC2V_SCC_RX (PCC2V_SCC_TX + 1) |
| 85 | |
| 86 | #if 0 |
| 87 | /* |
| 88 | * Vaddrs for interrupt mask and pri registers |
| 89 | */ |
| 90 | extern u_int8_t *volatile pcc2intr_mask; |
| 91 | extern u_int8_t *volatile pcc2intr_ipl; |
| 92 | #endif |
| 93 | |
| 94 | /* |
| 95 | * We lock off our interrupt vector at 0x50. |
| 96 | */ |
| 97 | #define PCC2_VECBASE 0x50 |
| 98 | #define PCC2_NVEC 0x10 |
| 99 | |
| 100 | #define PCC2_TCTL_CEN 0x01 |
| 101 | #define PCC2_TCTL_COC 0x02 |
| 102 | #define PCC2_TCTL_COVF 0x04 |
| 103 | #define PCC2_TCTL_OVF 0xf0 |
| 104 | |
| 105 | #define PCC2_GPIO_PLTY 0x80 |
| 106 | #define PCC2_GPIO_EL 0x40 |
| 107 | |
| 108 | #define PCC2_GPIOCR_OE 0x2 |
| 109 | #define PCC2_GPIOCR_O 0x1 |
| 110 | |
| 111 | #define PCC2_SCC_AVEC 0x08 |
| 112 | |
| 113 | #define PCC2_SC_INHIBIT (0 << 6) |
| 114 | #define PCC2_SC_SNOOP (1 << 6) |
| 115 | #define PCC2_SC_INVAL (2 << 6) |
| 116 | #define PCC2_SC_RESV (3 << 6) |
| 117 | |
| 118 | #define pcc2_timer_us2lim(us) (us) /* timer increments in "us" */ |
| 119 | |
| 120 | #define PCC2_IRQ_IPL 0x07 |
| 121 | #define PCC2_IRQ_ICLR 0x08 |
| 122 | #define PCC2_IRQ_IEN 0x10 |
| 123 | #define PCC2_IRQ_INT 0x20 |
| 124 | |
| 125 | /* Tick Timer Interrupt Control Register */ |
| 126 | #define PCC2_TTIRQ_INT 0x20 |
| 127 | #define PCC2_TTIRQ_IEN 0x10 |
| 128 | #define PCC2_TTIRQ_ICLR 0x08 |
| 129 | #define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ |
| 130 | |
| 131 | #define PCC2_IEERR_SCLR 0x01 |
| 132 | |
| 133 | #define PCC2_GENCTL_FAST 0x01 |
| 134 | #define PCC2_GENCTL_IEN 0x02 |
| 135 | #define PCC2_GENCTL_C040 0x03 |
| 136 | |
| 137 | #endif /* MVME_PCCTWOREG_H */ |
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