46 |
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47 |
/* PCI IO space */ |
/* PCI IO space */ |
48 |
#define MPC_PCI_IO_BASE 0xfec00000 |
#define MPC_PCI_IO_BASE 0xfec00000 |
49 |
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#if 0 |
50 |
#define MPC_PCI_IO_START 0xf8800000 /* for allocation */ |
#define MPC_PCI_IO_START 0xf8800000 /* for allocation */ |
51 |
#define MPC_PCI_IO_END 0xfeffffff |
#define MPC_PCI_IO_END 0xfeffffff |
52 |
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#endif |
53 |
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54 |
/* PCI config space */ |
/* PCI config space */ |
55 |
#define MPC_PCICFGADR 0xfee00000 |
#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
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#define MPC_PCI_CONFIG_ENABLE 0x80000000 |
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#define MPC_PCICFGDATA 0xfee00004 |
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56 |
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57 |
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#if 0 |
58 |
/* Config space regs */ |
/* Config space regs */ |
59 |
#define MPC_PCI_BRDGERR 0x48 |
#define MPC_PCI_BRDGERR 0x48 |
60 |
#define MPC_PCI_CLEARERR 0x0000ff00 |
#define MPC_PCI_CLEARERR 0x0000ff00 |
86 |
#define MPC_PTM1_MEMSIZE 0xff400034 |
#define MPC_PTM1_MEMSIZE 0xff400034 |
87 |
#define MPC_PTM2_LOCAL 0xff400038 |
#define MPC_PTM2_LOCAL 0xff400038 |
88 |
#define MPC_PTM2_MEMSIZE 0xff40003c |
#define MPC_PTM2_MEMSIZE 0xff40003c |
89 |
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#endif |
90 |
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91 |
/* serial ports */ |
/* serial ports */ |
92 |
#define MPC_COM0 0xfc004500ULL |
#define MPC_COM0 0xfc004500ULL |
93 |
#define MPC_COM1 0xfc004600ULL |
#define MPC_COM1 0xfc004600ULL |
94 |
#define MPC_COM_SPEED(bus) ((bus) / (2 * 4)) |
#define MPC_COM_SPEED(bus) ((bus) / (2 * 4)) |
95 |
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96 |
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#if 0 |
97 |
/* processor interface registers */ |
/* processor interface registers */ |
98 |
#define MPC_PIF_CFGADR 0xff500000 |
#define MPC_PIF_CFGADR 0xff500000 |
99 |
#define MPC_PIF_CFG_PRIFOPT1 0x00 |
#define MPC_PIF_CFG_PRIFOPT1 0x00 |
115 |
#define MPC_PIF_CFG_BEAR 0x4c |
#define MPC_PIF_CFG_BEAR 0x4c |
116 |
#define MPC_PIF_CFG_PLBSWRINT 0x80 |
#define MPC_PIF_CFG_PLBSWRINT 0x80 |
117 |
#define MPC_PIF_CFGDATA 0xff500004 |
#define MPC_PIF_CFGDATA 0xff500004 |
118 |
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#endif |
119 |
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120 |
/* interrupt controller */ |
/* interrupt controller */ |
121 |
#define MPC_UIC_BASE 0xff500880 |
#define MPC_UIC_BASE 0xfec00000 |
122 |
#define MPC_UIC_SIZE 0x00000024 |
#define MPC_UIC_SIZE 0x00000024 |
123 |
#define MPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ |
#define MPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ |
124 |
#define MPC_UIC_SRS 0x00000004 /* UIC status (set) */ |
#define MPC_UIC_SRS 0x00000004 /* UIC status (set) */ |
162 |
#define MPC_INTR_MASK(irq) (0x80000000 >> (irq)) |
#define MPC_INTR_MASK(irq) (0x80000000 >> (irq)) |
163 |
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164 |
#if 0 |
#if 0 |
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165 |
/* IIC */ |
/* IIC */ |
166 |
#define MPC_IIC0 0xfc020000 |
#define MPC_IIC0 0xfc020000 |
167 |
#define MPC_IIC1 0xfc030000 |
#define MPC_IIC1 0xfc030000 |