40 |
* POSSIBILITY OF SUCH DAMAGE. |
* POSSIBILITY OF SUCH DAMAGE. |
41 |
*/ |
*/ |
42 |
|
|
43 |
|
#if 0 |
44 |
/* PCI memory space */ |
/* PCI memory space */ |
45 |
#define MPC_PCI_MEM_BASE 0x80000000 |
#define MPC_PCI_MEM_BASE 0x80000000 |
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#if 0 |
|
46 |
#define MPC_PCI_MEM_END 0xf7ffffff |
#define MPC_PCI_MEM_END 0xf7ffffff |
47 |
#endif |
#endif |
48 |
|
|
49 |
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#if 0 |
50 |
/* PCI IO space */ |
/* PCI IO space */ |
51 |
#define MPC_PCI_IO_BASE 0xfec00000 |
#define MPC_PCI_IO_BASE 0xfec00000 |
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#if 0 |
|
52 |
#define MPC_PCI_IO_START 0xf8800000 /* for allocation */ |
#define MPC_PCI_IO_START 0xf8800000 /* for allocation */ |
53 |
#define MPC_PCI_IO_END 0xfeffffff |
#define MPC_PCI_IO_END 0xfeffffff |
54 |
#endif |
#endif |
55 |
|
|
56 |
/* PCI config space */ |
/* PCI config space */ |
57 |
#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
#define MPC10X_MAPB_CNFG_DATA 0xfec00000 |
58 |
|
|
59 |
#if 0 |
#if 0 |
60 |
/* Config space regs */ |
/* Config space regs */ |
120 |
#endif |
#endif |
121 |
|
|
122 |
/* interrupt controller */ |
/* interrupt controller */ |
123 |
#define MPC_UIC_BASE 0xfec00000 |
#define MPC_UIC_BASE 0xfc040000 |
124 |
#define MPC_UIC_SIZE 0x00000024 |
#define MPC_UIC_SIZE 0x00000024 |
125 |
#define MPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ |
#define MPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ |
126 |
#define MPC_UIC_SRS 0x00000004 /* UIC status (set) */ |
#define MPC_UIC_SRS 0x00000004 /* UIC status (set) */ |