/[gxemul]/trunk/src/include/mk48txxreg.h
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Contents of /trunk/src/include/mk48txxreg.h

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (12 years ago) by dpavlin
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File size: 5047 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /* GXemul: $Id: mk48txxreg.h,v 1.1 2006/01/17 05:55:58 debug Exp $ */
2 /* $NetBSD: mk48txxreg.h,v 1.7 2003/11/01 22:41:42 tsutsui Exp $ */
3
4 #ifndef MK48TXXREG_H
5 #define MK48TXXREG_H
6
7 /*-
8 * Copyright (c) 2000 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Paul Kranenburg.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the NetBSD
25 * Foundation, Inc. and its contributors.
26 * 4. Neither the name of The NetBSD Foundation nor the names of its
27 * contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
31 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
34 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43 /*
44 * Mostek MK48Txx clocks.
45 *
46 * The MK48T02 has 2KB of non-volatile memory. The time-of-day clock
47 * registers start at offset 0x7f8.
48 *
49 * The MK48T08 and MK48T18 have 8KB of non-volatile memory
50 *
51 * The MK48T59 also has 8KB of non-volatile memory but in addition it
52 * has a battery low detection bit and a power supply wakeup alarm for
53 * power management. It's at offset 0x1ff0 in the NVRAM.
54 */
55
56 /*
57 * Mostek MK48TXX register definitions
58 */
59
60 /*
61 * The first bank of eight registers at offset (nvramsz - 16) is
62 * available only on more recent (which??) MK48Txx models.
63 */
64 #define MK48TXX_IFLAGS 0 /* flags */
65 /* 1 unused on MK48T59 */
66 #define MK48TXX_IASEC 2 /* alarm seconds (0..59; BCD) */
67 #define MK48TXX_IAMIN 3 /* alarm minutes (0..59; BCD) */
68 #define MK48TXX_IAHOUR 4 /* alarm hour (0..23; BCD) */
69 #define MK48TXX_IADAY 5 /* alarm day (1..31; BCD) */
70 #define MK48TXX_IINTR 6 /* interrupts */
71 #define MK48TXX_IWDOG 7 /* watchdog */
72 #define MK48TXX_ICSR 8 /* control register */
73 #define MK48TXX_ISEC 9 /* seconds (0..59; BCD) */
74 #define MK48TXX_IMIN 10 /* minutes (0..59; BCD) */
75 #define MK48TXX_IHOUR 11 /* hour (0..23; BCD) */
76 #define MK48TXX_IWDAY 12 /* weekday (1..7) */
77 #define MK48TXX_IDAY 13 /* day in month (1..31; BCD) */
78 #define MK48TXX_IMON 14 /* month (1..12; BCD) */
79 #define MK48TXX_IYEAR 15 /* year (0..99; BCD) */
80
81 /* Bits in the flags register */
82 #define MK48TXX_FLAGS_WDF 0x80 /* watchdog flag */
83 #define MK48TXX_FLAGS_ALARM 0x40 /* alarm flag */
84 #define MK48TXX_FLAGS_BATTLOW 0x10 /* battery low */
85
86 /* Bits in the interrupt register */
87 #define MK48TXX_INTR_AFE 0x80 /* alarm flag enable */
88 #define MK48TXX_INTR_ABE 0x20 /* alarm in battery backup enable */
89
90 /* Bits in the watchdog register */
91 #define MK48TXX_WDOG_WDS 0x80 /* watchdog steering */
92 #define MK48TXX_WDOG_BMB_MASK 0x7c /* watchdog multiplier bits */
93 #define MK48TXX_WDOG_BMB_SHIFT 2
94 #define MK48TXX_WDOG_RES_MASK 0x03 /* watchdog resolution bits */
95 #define MK48TXX_WDOG_RES_1_16S 0x00 /* 1/16 seconds */
96 #define MK48TXX_WDOG_RES_1_4S 0x01 /* 1/4 seconds */
97 #define MK48TXX_WDOG_RES_1S 0x02 /* 1 second */
98 #define MK48TXX_WDOG_RES_4S 0x03 /* 4 seconds */
99
100 /* Bits in the control register */
101 #define MK48TXX_CSR_WRITE 0x80 /* want to write */
102 #define MK48TXX_CSR_READ 0x40 /* want to read (freeze clock) */
103
104 /* Bit in the weekday register */
105 #define MK48TXX_WDAY_FT 0x40 /* freq test: toggle sec[0] at 512Hz */
106 /* next two are on MK48T59 only */
107 #define MK48TXX_WDAY_CEB 0x20 /* century enable */
108 #define MK48TXX_WDAY_CB 0x10 /* century bit */
109
110 /* Bit in the seconds register */
111 #define MK48TXX_SEC_STOP 0x80 /* stop the oscillator */
112
113 #define MK48T02_CLKSZ 2048
114 #define MK48T02_CLKOFF 0x7f0
115
116 #define MK48T08_CLKSZ 8192
117 #define MK48T08_CLKOFF 0x1ff0
118
119 #define MK48T18_CLKSZ 8192
120 #define MK48T18_CLKOFF 0x1ff0
121
122 #define MK48T59_CLKSZ 8192
123 #define MK48T59_CLKOFF 0x1ff0
124
125 #endif /* MK48TXXREG_H */

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