/[gxemul]/trunk/src/include/mips_cpu_types.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC
# Line 2  Line 2 
2  #define MIPS_CPU_TYPES_H  #define MIPS_CPU_TYPES_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: mips_cpu_types.h,v 1.13 2006/01/11 19:20:08 debug Exp $   *  $Id: mips_cpu_types.h,v 1.17 2006/05/21 11:15:25 debug Exp $
32   *   *
33   *  MIPS CPU types.   *  MIPS CPU types.
34   */   */
# Line 36  Line 36 
36  #include <misc.h>  #include <misc.h>
37    
38  /*  MIPS CPU types:  */  /*  MIPS CPU types:  */
39  #include "cpuregs.h"  #include "mips_cpuregs.h"
40    
41  #define EXC3K           3  #define EXC3K           3
42  #define EXC4K           4  #define EXC4K           4
# Line 67  Line 67 
67   */   */
68    
69  #define MIPS_CPU_TYPE_DEFS      {       \  #define MIPS_CPU_TYPE_DEFS      {       \
70          { "R2000",      MIPS_R2000, 0x00,       NOLLSC, EXC3K, MMU3K,   1,      64, 1,13,2,1,13,2,1, 0, 0, 0 }, \          { "R2000",      MIPS_R2000, 0x00,       NOLLSC, EXC3K, MMU3K,   1, 0,   64, 1,13,2,1,13,2,1, 0, 0, 0 }, \
71          { "R2000A",     MIPS_R2000, 0x10,       NOLLSC, EXC3K, MMU3K,   1,      64, 1,13,2,1,13,2,1, 0, 0, 0 }, \          { "R2000A",     MIPS_R2000, 0x10,       NOLLSC, EXC3K, MMU3K,   1, 0,   64, 1,13,2,1,13,2,1, 0, 0, 0 }, \
72          { "R3000",      MIPS_R3000, 0x20,       NOLLSC, EXC3K, MMU3K,   1,      64, 1,12,2,1,12,2,1, 0, 0, 0 }, \          { "R3000",      MIPS_R3000, 0x20,       NOLLSC, EXC3K, MMU3K,   1, 0,   64, 1,12,2,1,12,2,1, 0, 0, 0 }, \
73          { "R3000A",     MIPS_R3000, 0x30,       NOLLSC, EXC3K, MMU3K,   1,      64, 1,13,2,1,13,2,1, 0, 0, 0 }, \          { "R3000A",     MIPS_R3000, 0x30,       NOLLSC, EXC3K, MMU3K,   1, 0,   64, 1,13,2,1,13,2,1, 0, 0, 0 }, \
74          { "R6000",      MIPS_R6000, 0x00,       0,      EXC3K, MMU3K,   2,      32, 1,16,2,2,16,2,2, 0, 0, 0 }, /*  instrs/cycle?  */  \          { "R6000",      MIPS_R6000, 0x00,       0,      EXC3K, MMU3K,   2, 0,   32, 1,16,2,2,16,2,2, 0, 0, 0 }, /*  instrs/cycle?  */  \
75          { "R4000",      MIPS_R4000, 0x00,       DCOUNT, EXC4K, MMU4K,   3,      48, 2,13,4,2,13,4,2,19, 6, 1 }, \          { "R4000",      MIPS_R4000, 0x00,       DCOUNT, EXC4K, MMU4K,   3, 0,   48, 2,13,4,2,13,4,2,19, 6, 1 }, \
76          { "R4000PC",    MIPS_R4000, 0x00,       DCOUNT, EXC4K, MMU4K,   3,      48, 2,13,4,2,13,4,2, 0, 6, 1 }, \          { "R4000PC",    MIPS_R4000, 0x00,       DCOUNT, EXC4K, MMU4K,   3, 0,   48, 2,13,4,2,13,4,2, 0, 6, 1 }, \
77          { "R10000",     MIPS_R10000,0x26,       0,      EXC4K, MMU10K,  4,      64, 4,15,6,2,15,5,2,20, 6, 1 }, \          { "R10000",     MIPS_R10000,0x26,       0,      EXC4K, MMU10K,  4, 0,   64, 4,15,6,2,15,5,2,20, 6, 1 }, \
78          { "R4200",      MIPS_R4200, 0x00,       0,      EXC4K, MMU4K,   3,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \          { "R4200",      MIPS_R4200, 0x00,       0,      EXC4K, MMU4K,   3, 0,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \
79          { "R4300",      MIPS_R4300, 0x00,       0,      EXC4K, MMU4K,   3,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \          { "R4300",      MIPS_R4300, 0x00,       0,      EXC4K, MMU4K,   3, 0,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \
80          { "R4100",      MIPS_R4100, 0x00,       0,      EXC4K, MMU4K,   3,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \          { "R4100",      MIPS_R4100, 0x00,       0,      EXC4K, MMU4K,   3, 0,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \
81          { "VR4102",     MIPS_R4100, 0x40,       NOFPU,  EXC4K, MMU4K,   3,      32, 2,12,0,0,10,0,0, 0, 0, 0 }, /*  TODO: Bogus?  */ \          { "VR4102",     MIPS_R4100, 0x40,       NOFPU,  EXC4K, MMU4K,   3, 0,   32, 2,12,0,0,10,0,0, 0, 0, 0 }, /*  TODO: Bogus?  */ \
82          { "VR4181",     MIPS_R4100, 0x50,       NOFPU,  EXC4K, MMU4K,   3,      32, 2,14,4,0,13,4,0, 0, 0, 0 }, \          { "VR4181",     MIPS_R4100, 0x50,       NOFPU,  EXC4K, MMU4K,   3, 0,   32, 2,14,4,0,13,4,0, 0, 0, 0 }, \
83          { "VR4121",     MIPS_R4100, 0x60,       NOFPU,  EXC4K, MMU4K,   3,      32, 2,14,4,0,13,4,0, 0, 0, 0 }, \          { "VR4121",     MIPS_R4100, 0x60,       NOFPU,  EXC4K, MMU4K,   3, 0,   32, 2,14,4,0,13,4,0, 0, 0, 0 }, \
84          { "VR4122",     MIPS_R4100, 0x70,       NOFPU,  EXC4K, MMU4K,   3,      32, 2,15,5,0,14,4,0, 0, 0, 0 }, \          { "VR4122",     MIPS_R4100, 0x70,       NOFPU,  EXC4K, MMU4K,   3, 0,   32, 2,15,5,0,14,4,0, 0, 0, 0 }, \
85          { "VR4131",     MIPS_R4100, 0x80,       NOFPU,  EXC4K, MMU4K,   3,      32, 2,14,5,0,14,5,0, 0, 0, 0 }, \          { "VR4131",     MIPS_R4100, 0x80,       NOFPU,  EXC4K, MMU4K,   3, 0,   32, 2,14,5,0,14,5,0, 0, 0, 0 }, \
86          { "R4400",      MIPS_R4000, 0x40,       DCOUNT, EXC4K, MMU4K,   3,      48, 2,14,4,1,14,4,1,20, 6, 1 }, \          { "R4400",      MIPS_R4000, 0x40,       DCOUNT, EXC4K, MMU4K,   3, 0,   48, 2,14,4,1,14,4,1,20, 6, 1 }, \
87          { "R4600",      MIPS_R4600, 0x00,       DCOUNT, EXC4K, MMU4K,   3,      48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \          { "R4600",      MIPS_R4600, 0x00,       DCOUNT, EXC4K, MMU4K,   3, 0,   48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
88          { "R4700",      MIPS_R4700, 0x00,       0,      EXC4K, MMU4K,   3,      48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \          { "R4700",      MIPS_R4700, 0x00,       0,      EXC4K, MMU4K,   3, 0,   48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \
89          { "R4650",      MIPS_R4650, 0x00,       0,      EXC4K, MMU4K,   3,      48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \          { "R4650",      MIPS_R4650, 0x00,       0,      EXC4K, MMU4K,   3, 0,   48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  No DCOUNT?  */ \
90          { "R8000",      MIPS_R8000, 0,          0,      EXC4K, MMU8K,   4,     192, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  192 tlb entries? or 384? instrs/cycle?  */ \          { "R8000",      MIPS_R8000, 0,          0,      EXC4K, MMU8K,   4, 0,  192, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  192 tlb entries? or 384? instrs/cycle?  */ \
91          { "R12000",     MIPS_R12000,0x23,       0,      EXC4K, MMU10K,  4,      64, 4,15,6,2,15,5,2,23, 6, 1 }, \          { "R12000",     MIPS_R12000,0x23,       0,      EXC4K, MMU10K,  4, 0,   64, 4,15,6,2,15,5,2,23, 6, 1 }, \
92          { "R14000",     MIPS_R14000,0,          0,      EXC4K, MMU10K,  4,      64, 4,15,6,2,15,5,2,22, 6, 1 }, \          { "R14000",     MIPS_R14000,0,          0,      EXC4K, MMU10K,  4, 0,   64, 4,15,6,2,15,5,2,22, 6, 1 }, \
93          { "R5000",      MIPS_R5000, 0x21,       DCOUNT, EXC4K, MMU4K,   4,      48, 4,15,5,2,15,5,2, 0, 0, 0 }, /*  2way I,D; instrs/cycle?  */ \          { "R5000",      MIPS_R5000, 0x21,       DCOUNT, EXC4K, MMU4K,   4, 0,   48, 4,15,5,2,15,5,2, 0, 0, 0 }, /*  2way I,D; instrs/cycle?  */ \
94          { "R5900",      MIPS_R5900, 0x20,       0,      EXC4K, MMU4K,   3,      48, 4,14,6,2,13,6,2, 0, 0, 0 }, /*  instrs/cycle?  */ \          { "R5900",      MIPS_R5900, 0x20,       0,      EXC4K, MMU4K,   3, 0,   48, 4,14,6,2,13,6,2, 0, 0, 0 }, /*  instrs/cycle?  */ \
95          { "TX3920",     MIPS_TX3900,0x30,       0,      EXC32, MMU32,   1,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: bogus?  */ \          { "TX3920",     MIPS_TX3900,0x30,       0,      EXC32, MMU32,   1, 0,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: bogus?  */ \
96          { "TX7901",     0x38,       0x01,       0,      EXC4K, MMU4K,  64,      48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: bogus?  */ \          { "TX7901",     MIPS_TX7900,0x01,       0,      EXC4K, MMU4K,   3, 1,   48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: bogus?  */ \
97          { "VR5432",     MIPS_R5400, 13,         0,      EXC4K, MMU4K,   4,      48, 4,15,0,0,15,0,0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? linesize? etc */ \          { "VR5432",     MIPS_R5400, 13,         0,      EXC4K, MMU4K,   4, 0,   48, 4,15,0,0,15,0,0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? linesize? etc */ \
98          { "RM5200",     MIPS_RM5200,0xa0,       0,      EXC4K, MMU4K,   4,      48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle?  */ \          { "RM5200",     MIPS_RM5200,0xa0,       0,      EXC4K, MMU4K,   4, 0,   48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle?  */ \
99          { "RM7000",     MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K,   4,      48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize & assoc.? RM7000A? */ \          { "RM7000",     MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K,   4, 0,   48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize & assoc.? RM7000A? */ \
100          { "RM7900",     0x34 /*?*/,  0x0 /* ? */,DCOUNT,EXC4K, MMU4K,   4,      64, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize? assoc = 4ways for all  */ \          { "RM7900",     0x34 /*?*/,  0x0 /* ? */,DCOUNT,EXC4K, MMU4K,   4, 0,   64, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize? assoc = 4ways for all  */ \
101          { "RM9000",     0x34 /*?*/,  0x0 /* ? */,DCOUNT,EXC4K, MMU4K,   4,      48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  This is totally bogus  */ \          { "RM9000",     0x34 /*?*/,  0x0 /* ? */,DCOUNT,EXC4K, MMU4K,   4, 0,   48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  This is totally bogus  */ \
102          { "RC32334",    MIPS_RC32300,0x00,      0,      EXC32, MMU4K,  32,      16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \          { "RC32334",    MIPS_RC32300,0x00,      0,      EXC32, MMU4K,  32, 1,   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
103          { "4Kc",        0x100+MIPS_4Kc, 1,      0,      EXC32, MMU32,  32,      16, 4,14,4,2,14,4,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \          { "4Kc",        0x100+MIPS_4Kc, 1,      0,      EXC32, MMU32,  32, 1,   16, 4,14,4,2,14,4,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \
104          { "5Kc",        0x100+MIPS_5Kc, 1,      0,      EXC64, MMU64,  64,      48, 4,15,5,2,15,5,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \          { "5Kc",        0x100+MIPS_5Kc, 1,      0,      EXC64, MMU64,  64, 1,   48, 4,15,5,2,15,5,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \
105          { "BCM4710",    0x000240,   0x00,       0,      EXC32, MMU32,  32,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: this is just bogus  */ \          { "BCM4710",    0x000240,   0x00,       0,      EXC32, MMU32,  32, 1,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: this is just bogus  */ \
106          { "BCM4712",    0x000290,   0x07,       0,      EXC32, MMU32,  32,      32, 2,13,4,1,12,4,1, 0, 0, 0 }, /*  2ways I, 2ways D  */ \          { "BCM4712",    0x000290,   0x07,       0,      EXC32, MMU32,  32, 1,   32, 2,13,4,1,12,4,1, 0, 0, 0 }, /*  2ways I, 2ways D  */ \
107          { "AU1000",     0x000301,   0x00,       0,      EXC32, MMU32,  32,      32, 2,14,5,2,14,5,2, 0, 0, 0 }, /*  TODO: this is just bogus  */ \          { "AU1000",     0x00302,    0x01,       0,      EXC32, MMU32,  32, 1,   32, 2,14,5,2,14,5,2, 0, 0, 0 }, /*  TODO: this is just bogus  */ \
108          { "AU1500",     0x010301,   0x00,       0,      EXC32, MMU32,  32,      32, 2,14,5,2,14,5,2, 0, 0, 0 }, /*  TODO: this is just bogus  */ \          { "AU1500",     0x10302,    0x02,       0,      EXC32, MMU32,  32, 1,   32, 2,14,5,4,14,5,4, 0, 0, 0 }, \
109          { "AU1100",     0x020301,   0x00,       0,      EXC32, MMU32,  32,      32, 2,14,5,2,14,5,2, 0, 0, 0 }, /*  TODO: this is just bogus  */ \          { "AU1100",     0x20302,    0x01,       0,      EXC32, MMU32,  32, 1,   32, 2,14,5,2,14,5,2, 0, 0, 0 }, /*  TODO: this is just bogus  */ \
110          { "SB1",        0x000401,   0x00,       0,      EXC64, MMU64,  64,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: this is just bogus  */ \          { "SB1",        0x000401,   0x00,       0,      EXC64, MMU64,  64, 1,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: this is just bogus  */ \
111          { "SR7100",     0x000504,   0x00,       0,      EXC64, MMU64,  64,      32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: this is just bogus  */ \          { "SR7100",     0x000504,   0x00,       0,      EXC64, MMU64,  64, 1,   32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  TODO: this is just bogus  */ \
112          { "Allegrex",   0x000000,   0x00,       0,      EXC32, MMU32,   2,       4, 1,14,6,2,14,6,2, 0, 0, 0 }, \          { "Allegrex",   0x000000,   0x00,       0,      EXC32, MMU32,   2, 0,    4, 1,14,6,2,14,6,2, 0, 0, 0 }, \
113          { NULL,         0,          0,          0,      0,     0,       0,       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }          { NULL,         0,          0,          0,      0,     0,       0,       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
114    
115  #endif  /*  MIPS_CPU_TYPES_H  */  #endif  /*  MIPS_CPU_TYPES_H  */
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