/[gxemul]/trunk/src/include/mips_cpu_types.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 14 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  #ifndef CPU_TYPES_H  #ifndef MIPS_CPU_TYPES_H
2  #define CPU_TYPES_H  #define MIPS_CPU_TYPES_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: mips_cpu_types.h,v 1.10 2005/09/23 10:36:03 debug Exp $   *  $Id: mips_cpu_types.h,v 1.13 2006/01/11 19:20:08 debug Exp $
32   *   *
33   *  MIPS CPU types.   *  MIPS CPU types.
34   */   */
# Line 97  Line 97 
97          { "VR5432",     MIPS_R5400, 13,         0,      EXC4K, MMU4K,   4,      48, 4,15,0,0,15,0,0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? linesize? etc */ \          { "VR5432",     MIPS_R5400, 13,         0,      EXC4K, MMU4K,   4,      48, 4,15,0,0,15,0,0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? linesize? etc */ \
98          { "RM5200",     MIPS_RM5200,0xa0,       0,      EXC4K, MMU4K,   4,      48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle?  */ \          { "RM5200",     MIPS_RM5200,0xa0,       0,      EXC4K, MMU4K,   4,      48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle?  */ \
99          { "RM7000",     MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K,   4,      48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize & assoc.? RM7000A? */ \          { "RM7000",     MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K,   4,      48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize & assoc.? RM7000A? */ \
100          { "RM7900",     0 /*TODO*/, 0x0 /* ? */,DCOUNT, EXC4K, MMU4K,   4,      64, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize? assoc = 4ways for all  */ \          { "RM7900",     0x34 /*?*/,  0x0 /* ? */,DCOUNT,EXC4K, MMU4K,   4,      64, 4,14,5,1,14,5,1,18, 6, 1 }, /*  instrs/cycle? cachelinesize? assoc = 4ways for all  */ \
101          { "RM9000",     0x34,       0x0 /* ? */,DCOUNT, EXC4K, MMU4K,   4,      48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  This is totally bogus  */ \          { "RM9000",     0x34 /*?*/,  0x0 /* ? */,DCOUNT,EXC4K, MMU4K,   4,      48, 4,14,5,1,14,5,1,18, 6, 1 }, /*  This is totally bogus  */ \
102          { "RC32334",    MIPS_RC32300,0x00,      0,      EXC32, MMU4K,  32,      16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \          { "RC32334",    MIPS_RC32300,0x00,      0,      EXC32, MMU4K,  32,      16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
103          { "4Kc",        0x100+MIPS_4Kc, 1,      0,      EXC32, MMU32,  32,      16, 4,14,4,2,14,4,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \          { "4Kc",        0x100+MIPS_4Kc, 1,      0,      EXC32, MMU32,  32,      16, 4,14,4,2,14,4,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \
104          { "5Kc",        0x100+MIPS_5Kc, 1,      0,      EXC64, MMU64,  64,      48, 4,15,5,2,15,5,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \          { "5Kc",        0x100+MIPS_5Kc, 1,      0,      EXC64, MMU64,  64,      48, 4,15,5,2,15,5,2, 0, 0, 0 }, /*  DCOUNT?  instrs/cycle? BOGUS, TODO  */ \
# Line 112  Line 112 
112          { "Allegrex",   0x000000,   0x00,       0,      EXC32, MMU32,   2,       4, 1,14,6,2,14,6,2, 0, 0, 0 }, \          { "Allegrex",   0x000000,   0x00,       0,      EXC32, MMU32,   2,       4, 1,14,6,2,14,6,2, 0, 0, 0 }, \
113          { NULL,         0,          0,          0,      0,     0,       0,       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }          { NULL,         0,          0,          0,      0,     0,       0,       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
114    
115  #endif  /*  CPU_TYPES_H  */  #endif  /*  MIPS_CPU_TYPES_H  */
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