/[gxemul]/trunk/src/include/mips_cpu_types.h
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Contents of /trunk/src/include/mips_cpu_types.h

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Revision 10 - (show annotations)
Mon Oct 8 16:18:27 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 7224 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.815 2005/06/27 23:04:35 debug Exp $
20050617	Experimenting some more with netbooting OpenBSD/sgi. Adding
		a hack which allows emulated ethernet networks to be
		distributed across multiple emulator processes.
20050618	Minor updates (documentation, dummy YAMON emulation, etc).
20050620	strcpy/strcat -> strlcpy/strlcat updates.
		Some more progress on evbmips (Malta).
20050621	Adding a section to doc/configfiles.html about ethernet
		emulation across multiple hosts.
		Beginning the work on the ARM translation engine (using the
		dynamic-but-not-binary translation method).
		Fixing a bintrans bug: 0x9fc00000 should always be treated as
		PROM area, just as 0xbfc00000 is.
		Minor progress on Malta emulation (the PCI-ISA bus).
20050622	NetBSD/evbmips can now be installed (using another emulated
		machine) and run (including userland and so on). :-)
		Spliting up the bintrans haddr_entry field into two (one for
		read, one for write). Probably not much of a speed increase,
		though.
		Updating some NetBSD 2.0 -> 2.0.2 in the documentation.
20050623	Minor updates (documentation, the TODO file, etc).
		gzipped kernels are now always automagically gunzipped when
		loaded.
20050624	Adding a dummy Playstation Portable (PSP) mode, just barely
		enough to run Hello World (in weird colors :-).
		Removing the -b command line option; old bintrans is enabled
		by default instead. It makes more sense.
		Trying to finally fix the non-working performance measurement
		thing (instr/second etc).
20050625	Continuing on the essential basics for ARM emulation. Two
		instructions seem to work, a branch and a simple "mov". (The
		mov arguments are not correct yet.) Performance is definitely
		reasonable.
		Various other minor updates.
		Adding the ARM "bl" instruction.
		Adding support for combining multiple ARM instructions into one
		function call. ("mov" + "mov" is the only one implemented so
		far, but it seems to work.)
		Cleaning up some IP32 interrupt things (crime/mace); disabling
		the PS/2 keyboard controller on IP32, so that NetBSD/sgimips
		boots into userland again.
20050626	Finally! NetBSD/sgimips netboots. Adding instructions to
		doc/guestoses.html on how to set up an nfs server etc.
		Various other minor fixes.
		Playstation Portable ".pbp" files can now be used directly.
		(The ELF part of the .pbp is extracted transparently.)
		Converting some sprintf -> snprintf.
		Adding some more instructions to the ARM disassembler.
20050627	More ARM updates. Adding some simple ldr(b), str(b),
		cmps, and conditional branch instructions, enough to run
		a simple Hello World program.
		All ARM instructions are now inlined/generated for all possible
		condition codes.
		Adding add and sub, and more load/store instructions.
		Removing dummy files: cpu_alpha.c, cpu_hppa.c, and cpu_sparc.c.
		Some minor documentation updates; preparing for a 0.3.4
		release. Updating some URLs.

==============  RELEASE 0.3.4  ==============
1 #ifndef CPU_TYPES_H
2 #define CPU_TYPES_H
3
4 /*
5 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: mips_cpu_types.h,v 1.5 2005/06/24 09:33:37 debug Exp $
32 *
33 * MIPS CPU types.
34 */
35
36 #include <misc.h>
37
38 /* MIPS CPU types: */
39 #include "cpuregs.h"
40
41 #define EXC3K 3
42 #define EXC4K 4
43 #define EXC32 32
44 #define EXC64 64
45
46 #define MMU3K 3
47 #define MMU4K 4
48 #define MMU8K 8
49 #define MMU10K 10
50 #define MMU32 32
51 #define MMU64 64
52
53 /* Bit-field values for the flags field: */
54 #define NOLLSC 1
55 #define DCOUNT 2
56 #define NOFPU 4
57
58 /*
59 * ---------------------------------------------------------------------------
60 * Please do NOT use this list as a definite source for
61 * PrID numbers, cache sizes, or anything like that!
62 * ---------------------------------------------------------------------------
63 *
64 * These numbers are gathered from various other places (manuals, mailing list
65 * posts, and from source code from various operating systems), and are not
66 * necessarily correct.
67 */
68
69 #define MIPS_CPU_TYPE_DEFS { \
70 { "R2000", MIPS_R2000, 0x00, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,13, 2, 2, 0, 0 }, \
71 { "R2000A", MIPS_R2000, 0x10, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,13, 2, 2, 0, 0 }, \
72 { "R3000", MIPS_R3000, 0x20, NOLLSC, EXC3K, MMU3K, 1, 64, 1,12,12, 2, 2, 0, 0 }, \
73 { "R3000A", MIPS_R3000, 0x30, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,13, 2, 2, 0, 0 }, \
74 { "R6000", MIPS_R6000, 0x00, 0, EXC3K, MMU3K, 2, 32, 1,16,16, 2, 2, 0, 0 }, /* instrs/cycle? */ \
75 { "R4000", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2,13,13, 4, 4,19, 6 }, \
76 { "R4000PC", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2,13,13, 4, 4, 0, 6 }, \
77 { "R10000", MIPS_R10000,0x26, 0, EXC4K, MMU10K, 4, 64, 4,15,15, 6, 5,20, 6 }, /* 2way I,D,Secondary */ \
78 { "R4200", MIPS_R4200, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
79 { "R4300", MIPS_R4300, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
80 { "R4100", MIPS_R4100, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
81 { "VR4102", MIPS_R4100, 0x40, NOFPU, EXC4K, MMU4K, 3, 32, 2,12,10, 0, 0, 0, 0 }, /* TODO: Bogus? */ \
82 { "VR4181", MIPS_R4100, 0x50, NOFPU, EXC4K, MMU4K, 3, 32, 2,12,12, 0, 0, 0, 0 }, /* TODO: Bogus? */ \
83 { "VR4121", MIPS_R4100, 0x60, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,13, 0, 0, 0, 0 }, /* TODO: Bogus? */ \
84 { "VR4122", MIPS_R4100, 0x70, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,14, 0, 0, 0, 0 }, /* TODO: Bogus? */ \
85 { "VR4131", MIPS_R4100, 0x80, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,14, 0, 0, 0, 0 }, /* TODO: Bogus? */ \
86 { "R4400", MIPS_R4000, 0x40, DCOUNT, EXC4K, MMU4K, 3, 48, 2,14,14, 4, 4,20, 6 }, /* direct mapped I,D,Sec */ \
87 { "R4600", MIPS_R4600, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0 }, \
88 { "R4700", MIPS_R4700, 0x00, 0, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
89 { "R4650", MIPS_R4650, 0x00, 0, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
90 { "R8000", MIPS_R8000, 0, 0, EXC4K, MMU8K, 4, 192, 2, 0, 0, 0, 0, 0, 0 }, /* 192 tlb entries? or 384? instrs/cycle? */ \
91 { "R12000", MIPS_R12000,0x23, 0, EXC4K, MMU10K, 4, 64, 4,15,15, 6, 5,23, 6 }, \
92 { "R14000", MIPS_R14000,0, 0, EXC4K, MMU10K, 4, 64, 4,15,15, 6, 5,22, 6 }, \
93 { "R5000", MIPS_R5000, 0x21, DCOUNT, EXC4K, MMU4K, 4, 48, 4,15,15, 5, 5, 0, 0 }, /* 2way I,D; instrs/cycle? */ \
94 { "R5900", MIPS_R5900, 0x20, 0, EXC4K, MMU4K, 3, 48, 4,14,13, 6, 6, 0, 0 }, /* instrs/cycle? */ \
95 { "TX3920", MIPS_TX3900,0x30, 0, EXC32, MMU32, 1, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \
96 { "TX7901", 0x38, 0x01, 0, EXC4K, MMU4K, 64, 48, 4, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \
97 { "VR5432", MIPS_R5400, 13, 0, EXC4K, MMU4K, -1, -1, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \
98 { "RM5200", MIPS_RM5200,0xa0, 0, EXC4K, MMU4K, 4, 48, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \
99 { "RM7000", MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 48, 4,14,14, 5, 5,18, 6 }, /* instrs/cycle? cachelinesize & assoc.? RM7000A? */ \
100 { "RM7900", 0 /*TODO*/, 0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 64, 4,14,14, 5, 5,18, 6 }, /* instrs/cycle? cachelinesize? assoc = 4ways for all */ \
101 { "RM9000", 0x34, 0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 48, 4,14,14, 5, 5,18, 6 }, /* This is totally bogus */ \
102 { "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 16, 1, 0, 0, 0, 0, 0, 0 }, \
103 { "4Kc", 0x100+MIPS_4Kc, 1 /*?*/,0, EXC32, MMU32, 32, 48, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \
104 { "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 48, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \
105 { "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
106 { "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 32, 2,13,12, 4, 4, 0, 0 }, /* 2ways I, 2ways D */ \
107 { "AU1000", 0x000301, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
108 { "AU1500", 0x010301, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
109 { "AU1100", 0x020301, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
110 { "SB1", 0x000401, 0x00, 0, EXC64, MMU64, 64, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
111 { "SR7100", 0x000504, 0x00, 0, EXC64, MMU64, 64, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
112 { "Allegrex", 0x000000, 0x00, 0, EXC3K, MMU32, 2, 4, 1,14,14, 6, 6, 0, 0 }, \
113 { NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
114
115 #endif /* CPU_TYPES_H */
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