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dpavlin |
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#ifndef CPU_TYPES_H |
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#define CPU_TYPES_H |
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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: mips_cpu_types.h,v 1.4 2005/04/02 23:02:17 debug Exp $ |
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* |
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* MIPS CPU types. |
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*/ |
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#include <misc.h> |
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/* MIPS CPU types: */ |
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#include "cpuregs.h" |
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#define EXC3K 3 |
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#define EXC4K 4 |
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#define EXC32 32 |
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#define EXC64 64 |
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#define MMU3K 3 |
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#define MMU4K 4 |
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#define MMU8K 8 |
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#define MMU10K 10 |
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#define MMU32 32 |
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#define MMU64 64 |
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/* Bit-field values for the flags field: */ |
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#define NOLLSC 1 |
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#define DCOUNT 2 |
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#define NOFPU 4 |
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/* |
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* --------------------------------------------------------------------------- |
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* Please do NOT use this list as a definite source for |
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* PrID numbers, cache sizes, or anything like that! |
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* --------------------------------------------------------------------------- |
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* |
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* These numbers are gathered from various other places (manuals, mailing list |
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* posts, and from source code from various operating systems), and are not |
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* necessarily correct. |
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*/ |
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#define MIPS_CPU_TYPE_DEFS { \ |
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{ "R2000", MIPS_R2000, 0x00, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,13, 2, 2, 0, 0 }, \ |
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{ "R2000A", MIPS_R2000, 0x10, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,13, 2, 2, 0, 0 }, \ |
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{ "R3000", MIPS_R3000, 0x20, NOLLSC, EXC3K, MMU3K, 1, 64, 1,12,12, 2, 2, 0, 0 }, \ |
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{ "R3000A", MIPS_R3000, 0x30, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,13, 2, 2, 0, 0 }, \ |
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{ "R6000", MIPS_R6000, 0x00, 0, EXC3K, MMU3K, 2, 32, 1,16,16, 2, 2, 0, 0 }, /* instrs/cycle? */ \ |
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{ "R4000", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2,13,13, 4, 4,19, 6 }, \ |
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{ "R4000PC", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2,13,13, 4, 4, 0, 6 }, \ |
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{ "R10000", MIPS_R10000,0x26, 0, EXC4K, MMU10K, 4, 64, 4,15,15, 6, 5,20, 6 }, /* 2way I,D,Secondary */ \ |
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{ "R4200", MIPS_R4200, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R4300", MIPS_R4300, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R4100", MIPS_R4100, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "VR4102", MIPS_R4100, 0x40, NOFPU, EXC4K, MMU4K, 3, 32, 2,12,10, 0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
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{ "VR4181", MIPS_R4100, 0x50, NOFPU, EXC4K, MMU4K, 3, 32, 2,12,12, 0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
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{ "VR4121", MIPS_R4100, 0x60, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,13, 0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
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{ "VR4122", MIPS_R4100, 0x70, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,14, 0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
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{ "VR4131", MIPS_R4100, 0x80, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,14, 0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
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{ "R4400", MIPS_R4000, 0x40, DCOUNT, EXC4K, MMU4K, 3, 48, 2,14,14, 4, 4,20, 6 }, /* direct mapped I,D,Sec */ \ |
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{ "R4600", MIPS_R4600, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0 }, \ |
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{ "R4700", MIPS_R4700, 0x00, 0, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R4650", MIPS_R4650, 0x00, 0, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R8000", MIPS_R8000, 0, 0, EXC4K, MMU8K, 4, 192, 2, 0, 0, 0, 0, 0, 0 }, /* 192 tlb entries? or 384? instrs/cycle? */ \ |
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{ "R12000", MIPS_R12000,0x23, 0, EXC4K, MMU10K, 4, 64, 4,15,15, 6, 5,23, 6 }, \ |
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{ "R14000", MIPS_R14000,0, 0, EXC4K, MMU10K, 4, 64, 4,15,15, 6, 5,22, 6 }, \ |
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{ "R5000", MIPS_R5000, 0x21, DCOUNT, EXC4K, MMU4K, 4, 48, 4,15,15, 5, 5, 0, 0 }, /* 2way I,D; instrs/cycle? */ \ |
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{ "R5900", MIPS_R5900, 0x20, 0, EXC4K, MMU4K, 3, 48, 4,14,13, 6, 6, 0, 0 }, /* instrs/cycle? */ \ |
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{ "TX3920", MIPS_TX3900,0x30, 0, EXC32, MMU32, 1, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \ |
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{ "TX7901", 0x38, 0x01, 0, EXC4K, MMU4K, 64, 48, 4, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \ |
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{ "VR5432", MIPS_R5400, 13, 0, EXC4K, MMU4K, -1, -1, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \ |
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{ "RM5200", MIPS_RM5200,0xa0, 0, EXC4K, MMU4K, 4, 48, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \ |
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{ "RM7000", MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 48, 4,14,14, 5, 5,18, 6 }, /* instrs/cycle? cachelinesize & assoc.? RM7000A? */ \ |
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{ "RM7900", 0 /*TODO*/, 0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 64, 4,14,14, 5, 5,18, 6 }, /* instrs/cycle? cachelinesize? assoc = 4ways for all */ \ |
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{ "RM9000", 0x34, 0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 48, 4,14,14, 5, 5,18, 6 }, /* This is totally bogus */ \ |
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{ "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 16, 1, 0, 0, 0, 0, 0, 0 }, \ |
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{ "4Kc", 0x100+MIPS_4Kc, 1 /*?*/,0, EXC32, MMU32, 32, 48, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 48, 4, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 32, 2,13,12, 4, 4, 0, 0 }, /* 2ways I, 2ways D */ \ |
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{ "AU1000", 0x000301, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "AU1500", 0x010301, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "AU1100", 0x020301, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "SB1", 0x000401, 0x00, 0, EXC64, MMU64, 64, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "SR7100", 0x000504, 0x00, 0, EXC64, MMU64, 64, 32, 2, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } |
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#endif /* CPU_TYPES_H */ |