/[gxemul]/trunk/src/include/mii.h
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Contents of /trunk/src/include/mii.h

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8784 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============
1 /* GXemul: $Id: mii.h,v 1.1 2005/11/25 02:34:24 debug Exp $ */
2 /* $NetBSD: mii.h,v 1.12 2005/02/27 00:27:31 perry Exp $ */
3
4 #ifndef _DEV_MII_MII_H_
5 #define _DEV_MII_MII_H_
6
7 /*
8 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
9 *
10 * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe,
11 * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by Manuel Bouyer.
24 * 4. The name of the author may not be used to endorse or promote products
25 * derived from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Registers common to all PHYs.
41 */
42
43 #define MII_NPHY 32 /* max # of PHYs per MII */
44
45 /*
46 * MII commands, used if a device must drive the MII lines
47 * manually.
48 */
49 #define MII_COMMAND_START 0x01
50 #define MII_COMMAND_READ 0x02
51 #define MII_COMMAND_WRITE 0x01
52 #define MII_COMMAND_ACK 0x02
53
54 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
55 #define BMCR_RESET 0x8000 /* reset */
56 #define BMCR_LOOP 0x4000 /* loopback */
57 #define BMCR_SPEED0 0x2000 /* speed selection (LSB) */
58 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */
59 #define BMCR_PDOWN 0x0800 /* power down */
60 #define BMCR_ISO 0x0400 /* isolate */
61 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */
62 #define BMCR_FDX 0x0100 /* Set duplex mode */
63 #define BMCR_CTEST 0x0080 /* collision test */
64 #define BMCR_SPEED1 0x0040 /* speed selection (MSB) */
65
66 #define BMCR_S10 0x0000 /* 10 Mb/s */
67 #define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */
68 #define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */
69
70 #define BMCR_SPEED(x) ((x) & (BMCR_SPEED0|BMCR_SPEED1))
71
72 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
73 #define BMSR_100T4 0x8000 /* 100 base T4 capable */
74 #define BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
75 #define BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
76 #define BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
77 #define BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
78 #define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
79 #define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
80 #define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */
81 #define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */
82 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */
83 #define BMSR_RFAULT 0x0010 /* Link partner fault */
84 #define BMSR_ANEG 0x0008 /* Autonegotiation capable */
85 #define BMSR_LINK 0x0004 /* Link status */
86 #define BMSR_JABBER 0x0002 /* Jabber detected */
87 #define BMSR_EXTCAP 0x0001 /* Extended capability */
88
89 /*
90 * Note that the EXTSTAT bit indicates that there is extended status
91 * info available in register 15, but 802.3 section 22.2.4.3 also
92 * states that that all 1000 Mb/s capable PHYs will set this bit to 1.
93 */
94
95 #define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
96 BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX)
97
98 /*
99 * Convert BMSR media capabilities to ANAR bits for autonegotiation.
100 * Note the shift chopps off the BMSR_ANEG bit.
101 */
102 #define BMSR_MEDIA_TO_ANAR(x) (((x) & BMSR_MEDIAMASK) >> 6)
103
104 #define MII_PHYIDR1 0x02 /* ID register 1 (ro) */
105
106 #define MII_PHYIDR2 0x03 /* ID register 2 (ro) */
107 #define IDR2_OUILSB 0xfc00 /* OUI LSB */
108 #define IDR2_MODEL 0x03f0 /* vendor model */
109 #define IDR2_REV 0x000f /* vendor revision */
110
111 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */
112 /* section 28.2.4.1 and 37.2.6.1 */
113 #define ANAR_NP 0x8000 /* Next page (ro) */
114 #define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */
115 #define ANAR_RF 0x2000 /* remote fault (ro) */
116 #define ANAR_FC 0x0400 /* local device supports PAUSE */
117 #define ANAR_T4 0x0200 /* local device supports 100bT4 */
118 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
119 #define ANAR_TX 0x0080 /* local device supports 100bTx */
120 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */
121 #define ANAR_10 0x0020 /* local device supports 10bT */
122 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */
123
124 #define ANAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */
125 #define ANAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */
126 #define ANAR_X_PAUSE_NONE (0 << 10)
127 #define ANAR_X_PAUSE_SYM (1 << 10)
128 #define ANAR_X_PAUSE_ASYM (2 << 10)
129 #define ANAR_X_PAUSE_TOWARDS (3 << 10)
130
131 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
132 /* section 28.2.4.1 and 37.2.6.1 */
133 #define ANLPAR_NP 0x8000 /* Next page (ro) */
134 #define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */
135 #define ANLPAR_RF 0x2000 /* remote fault (ro) */
136 #define ANLPAR_FC 0x0400 /* link partner supports PAUSE */
137 #define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
138 #define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
139 #define ANLPAR_TX 0x0080 /* link partner supports 100bTx */
140 #define ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
141 #define ANLPAR_10 0x0020 /* link partner supports 10bT */
142 #define ANLPAR_CSMA 0x0001 /* protocol selector CSMA/CD */
143
144 #define ANLPAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */
145 #define ANLPAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */
146 #define ANLPAR_X_PAUSE_MASK (3 << 10)
147 #define ANLPAR_X_PAUSE_NONE (0 << 10)
148 #define ANLPAR_X_PAUSE_SYM (1 << 10)
149 #define ANLPAR_X_PAUSE_ASYM (2 << 10)
150 #define ANLPAR_X_PAUSE_TOWARDS (3 << 10)
151
152 #define MII_ANER 0x06 /* Autonegotiation expansion (ro) */
153 /* section 28.2.4.1 and 37.2.6.1 */
154 #define ANER_MLF 0x0010 /* multiple link detection fault */
155 #define ANER_LPNP 0x0008 /* link parter next page-able */
156 #define ANER_NP 0x0004 /* next page-able */
157 #define ANER_PAGE_RX 0x0002 /* Page received */
158 #define ANER_LPAN 0x0001 /* link parter autoneg-able */
159
160 #define MII_ANNP 0x07 /* Autonegotiation next page */
161 /* section 28.2.4.1 and 37.2.6.1 */
162
163 #define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */
164 /* section 32.5.1 and 37.2.6.1 */
165
166 /* This is also the 1000baseT control register */
167 #define MII_100T2CR 0x09 /* 100base-T2 control register */
168 #define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */
169 #define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */
170 #define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */
171 #define GTCR_PORT_TYPE 0x0400 /* 1 = DCE, 0 = DTE (NIC) */
172 #define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
173 #define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
174
175 /* This is also the 1000baseT status register */
176 #define MII_100T2SR 0x0a /* 100base-T2 status register */
177 #define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */
178 #define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */
179 #define GTSR_LRS 0x2000 /* local rx status, 1 = ok */
180 #define GTSR_RRS 0x1000 /* remove rx status, 1 = ok */
181 #define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */
182 #define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */
183 #define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */
184 #define GTSR_IDLE_ERR 0x00ff /* IDLE error count */
185
186 #define MII_EXTSR 0x0f /* Extended status register */
187 #define EXTSR_1000XFDX 0x8000 /* 1000X full-duplex capable */
188 #define EXTSR_1000XHDX 0x4000 /* 1000X half-duplex capable */
189 #define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */
190 #define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */
191
192 #define EXTSR_MEDIAMASK (EXTSR_1000XFDX|EXTSR_1000XHDX| \
193 EXTSR_1000TFDX|EXTSR_1000THDX)
194
195 #endif /* _DEV_MII_MII_H_ */
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