/[gxemul]/trunk/src/include/memory.h
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revision 14 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 28 by dpavlin, Mon Oct 8 16:20:26 2007 UTC
# Line 2  Line 2 
2  #define MEMORY_H  #define MEMORY_H
3    
4  /*  /*
5   *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: memory.h,v 1.37 2005/09/22 09:07:00 debug Exp $   *  $Id: memory.h,v 1.51 2006/07/08 12:30:03 debug Exp $
32   *   *
33   *  Memory controller related functions.   *  Memory controller related functions.
34   */   */
# Line 40  Line 40 
40    
41    
42  #define DEFAULT_RAM_IN_MB               32  #define DEFAULT_RAM_IN_MB               32
43  #define MAX_DEVICES                     24  #define MAX_DEVICES                     26
   
 #define DEVICE_STATE_TYPE_INT           1  
 #define DEVICE_STATE_TYPE_UINT64_T      2  
44    
45  struct cpu;  struct cpu;
46  struct translation_page_entry;  struct translation_page_entry;
47    
 /*  For bintrans:  */  
 #define MAX_QUICK_JUMPS                 8  
   
48  struct memory {  struct memory {
49          uint64_t        physical_max;          uint64_t        physical_max;
50          void            *pagetable;          void            *pagetable;
# Line 64  struct memory { Line 58  struct memory {
58    
59          const char      *dev_name[MAX_DEVICES];          const char      *dev_name[MAX_DEVICES];
60          uint64_t        dev_baseaddr[MAX_DEVICES];          uint64_t        dev_baseaddr[MAX_DEVICES];
61            uint64_t        dev_endaddr[MAX_DEVICES];       /*  after the end!  */
62          uint64_t        dev_length[MAX_DEVICES];          uint64_t        dev_length[MAX_DEVICES];
63          int             dev_flags[MAX_DEVICES];          int             dev_flags[MAX_DEVICES];
64          void            *dev_extra[MAX_DEVICES];          void            *dev_extra[MAX_DEVICES];
65          int             (*dev_f[MAX_DEVICES])(struct cpu *,struct memory *,          int             (*dev_f[MAX_DEVICES])(struct cpu *,struct memory *,
66                              uint64_t,unsigned char *,size_t,int,void *);                              uint64_t,unsigned char *,size_t,int,void *);
         int             (*dev_f_state[MAX_DEVICES])(struct cpu *,  
                             struct memory *, void *extra, int wf, int nr,  
                             int *type, char **namep, void **data, size_t *len);  
67          unsigned char   *dev_dyntrans_data[MAX_DEVICES];          unsigned char   *dev_dyntrans_data[MAX_DEVICES];
68    
         int             dev_dyntrans_alignment;  
   
69          uint64_t        dev_dyntrans_write_low[MAX_DEVICES];          uint64_t        dev_dyntrans_write_low[MAX_DEVICES];
70          uint64_t        dev_dyntrans_write_high[MAX_DEVICES];          uint64_t        dev_dyntrans_write_high[MAX_DEVICES];
71    
72            int             dev_dyntrans_alignment;
         /*  
          *  NOTE/TODO: This bintrans was for MIPS only. Ugly. :-/  
          */  
   
         /*  
          *  translation_code_chunk_space is a large chunk of (linear) memory  
          *  where translated code chunks and translation_entrys are stored.  
          *  When this is filled, translation is restart from scratch (by  
          *  resetting translation_code_chunk_space_head to 0, and removing all  
          *  translation entries).  
          *  
          *  (Using a static memory region like this is somewhat inspired by  
          *  the QEMU web pages,  
          *  http://fabrice.bellard.free.fr/qemu/qemu-tech.html#SEC13)  
          */  
   
         unsigned char   *translation_code_chunk_space;  
         size_t          translation_code_chunk_space_head;  
   
         int             bintrans_32bit_only;  
   
         struct translation_page_entry **translation_page_entry_array;  
   
         unsigned char   *quick_jump_host_address[MAX_QUICK_JUMPS];  
         int             quick_jump_page_offset[MAX_QUICK_JUMPS];  
         int             n_quick_jumps;  
         int             quick_jumps_index;  
73  };  };
74    
75  #define BITS_PER_PAGETABLE      20  #define BITS_PER_PAGETABLE      20
76  #define BITS_PER_MEMBLOCK       20  #define BITS_PER_MEMBLOCK       20
77  #define MAX_BITS                40  #define MAX_BITS                40
78    
 #define MEM_READ                        0  
 #define MEM_WRITE                       1  
   
   
 #define CACHE_DATA                      0  
 #define CACHE_INSTRUCTION               1  
 #define CACHE_NONE                      2  
   
 #define CACHE_FLAGS_MASK                0x3  
   
 #define NO_EXCEPTIONS                   16  
 #define PHYSICAL                        32  
 #define NO_SEGMENTATION                 64      /*  for X86  */  
 #define MEMORY_USER_ACCESS              128     /*  for ARM, at least  */  
   
79    
80  /*  memory.c:  */  /*  memory.c:  */
81    #define MEM_PCI_LITTLE_ENDIAN   128
82  uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len);  uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len);
83  void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,  void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,
84          uint64_t data);          uint64_t data);
# Line 146  char *memory_conv_to_string(struct cpu * Line 95  char *memory_conv_to_string(struct cpu *
95  unsigned char *memory_paddr_to_hostaddr(struct memory *mem,  unsigned char *memory_paddr_to_hostaddr(struct memory *mem,
96          uint64_t paddr, int writeflag);          uint64_t paddr, int writeflag);
97    
 /*  memory_fast_v2h.c:  */  
 unsigned char *fast_vaddr_to_hostaddr(struct cpu *cpu, uint64_t vaddr,  
         int writeflag);  
   
 /*  MIPS stuff:  */  
 int translate_address_mmu3k(struct cpu *cpu, uint64_t vaddr,  
         uint64_t *return_addr, int flags);  
 int translate_address_mmu8k(struct cpu *cpu, uint64_t vaddr,  
         uint64_t *return_addr, int flags);  
 int translate_address_mmu10k(struct cpu *cpu, uint64_t vaddr,  
         uint64_t *return_addr, int flags);  
 int translate_address_mmu4100(struct cpu *cpu, uint64_t vaddr,  
         uint64_t *return_addr, int flags);  
 int translate_address_generic(struct cpu *cpu, uint64_t vaddr,  
         uint64_t *return_addr, int flags);  
98    
99    /*  Writeflag:  */
100    #define MEM_READ                        0
101    #define MEM_WRITE                       1
102    #define MEM_DOWNGRADE                   128
103    
104    /*  Misc. flags:  */
105    #define CACHE_DATA                      0
106    #define CACHE_INSTRUCTION               1
107    #define CACHE_NONE                      2
108    #define CACHE_FLAGS_MASK                0x3
109    #define NO_EXCEPTIONS                   16
110    #define PHYSICAL                        32
111    #define NO_SEGMENTATION                 64      /*  for X86  */
112    #define MEMORY_USER_ACCESS              128     /*  for ARM, at least  */
113    
114    /*  Dyntrans Memory flags:  */
115    #define DM_DEFAULT                              0
116    #define DM_DYNTRANS_OK                          1
117    #define DM_DYNTRANS_WRITE_OK                    2
118    #define DM_READS_HAVE_NO_SIDE_EFFECTS           4
119    #define DM_EMULATED_RAM                         8
120    
121  #define FLAG_WRITEFLAG          1  #define FLAG_WRITEFLAG          1
122  #define FLAG_NOEXCEPTIONS       2  #define FLAG_NOEXCEPTIONS       2
# Line 169  int translate_address_generic(struct cpu Line 124  int translate_address_generic(struct cpu
124    
125  int userland_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int userland_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
126          unsigned char *data, size_t len, int writeflag, int cache);          unsigned char *data, size_t len, int writeflag, int cache);
127  #define MEMORY_ACCESS_FAILED    0  #define MEMORY_ACCESS_FAILED            0
128  #define MEMORY_ACCESS_OK        1  #define MEMORY_ACCESS_OK                1
129    #define MEMORY_ACCESS_OK_WRITE          2
130    #define MEMORY_NOT_FULL_PAGE            256
131    
132  void memory_device_dyntrans_access(struct cpu *, struct memory *mem,  void memory_device_dyntrans_access(struct cpu *, struct memory *mem,
133          void *extra, uint64_t *low, uint64_t *high);          void *extra, uint64_t *low, uint64_t *high);
134    
135  void memory_device_register_statefunction(  #define DEVICE_ACCESS(x)        int dev_ ## x ## _access(struct cpu *cpu, \
136          struct memory *mem, void *extra,          struct memory *mem, uint64_t relative_addr, unsigned char *data,  \
137          int (*dev_f_state)(struct cpu *,          size_t len, int writeflag, void *extra)
138              struct memory *, void *extra, int wf, int nr,  
139              int *type, char **namep, void **data, size_t *len));  void memory_device_update_data(struct memory *mem, void *extra,
140            unsigned char *data);
141    
142  void memory_device_register(struct memory *mem, const char *,  void memory_device_register(struct memory *mem, const char *,
143          uint64_t baseaddr, uint64_t len, int (*f)(struct cpu *,          uint64_t baseaddr, uint64_t len, int (*f)(struct cpu *,
# Line 187  void memory_device_register(struct memor Line 145  void memory_device_register(struct memor
145          void *extra, int flags, unsigned char *dyntrans_data);          void *extra, int flags, unsigned char *dyntrans_data);
146  void memory_device_remove(struct memory *mem, int i);  void memory_device_remove(struct memory *mem, int i);
147    
148  /*  Bit flags:  */  uint64_t memory_checksum(struct memory *mem);
 #define MEM_DEFAULT                             0  
 #define MEM_DYNTRANS_OK                         1  
 #define MEM_DYNTRANS_WRITE_OK                   2  
 #define MEM_READING_HAS_NO_SIDE_EFFECTS         4  
149    
150    
151  #endif  /*  MEMORY_H  */  #endif  /*  MEMORY_H  */
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