/[gxemul]/trunk/src/include/memory.h
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Revision 20 - (hide annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 6726 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============
1 dpavlin 4 #ifndef MEMORY_H
2     #define MEMORY_H
3    
4     /*
5     * Copyright (C) 2004-2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 20 * $Id: memory.h,v 1.44 2005/11/22 16:26:38 debug Exp $
32 dpavlin 4 *
33     * Memory controller related functions.
34     */
35    
36     #include <sys/types.h>
37     #include <inttypes.h>
38    
39     #include "misc.h"
40    
41    
42     #define DEFAULT_RAM_IN_MB 32
43 dpavlin 20 #define MAX_DEVICES 26
44 dpavlin 4
45     #define DEVICE_STATE_TYPE_INT 1
46     #define DEVICE_STATE_TYPE_UINT64_T 2
47    
48     struct cpu;
49     struct translation_page_entry;
50    
51     /* For bintrans: */
52     #define MAX_QUICK_JUMPS 8
53    
54     struct memory {
55     uint64_t physical_max;
56     void *pagetable;
57    
58     int n_mmapped_devices;
59     int last_accessed_device;
60     /* The following two might speed up things a little bit. */
61     /* (actually maxaddr is the addr after the last address) */
62     uint64_t mmap_dev_minaddr;
63     uint64_t mmap_dev_maxaddr;
64    
65     const char *dev_name[MAX_DEVICES];
66     uint64_t dev_baseaddr[MAX_DEVICES];
67 dpavlin 18 uint64_t dev_endaddr[MAX_DEVICES]; /* after the end! */
68 dpavlin 4 uint64_t dev_length[MAX_DEVICES];
69     int dev_flags[MAX_DEVICES];
70     void *dev_extra[MAX_DEVICES];
71     int (*dev_f[MAX_DEVICES])(struct cpu *,struct memory *,
72     uint64_t,unsigned char *,size_t,int,void *);
73     int (*dev_f_state[MAX_DEVICES])(struct cpu *,
74     struct memory *, void *extra, int wf, int nr,
75     int *type, char **namep, void **data, size_t *len);
76 dpavlin 12 unsigned char *dev_dyntrans_data[MAX_DEVICES];
77 dpavlin 4
78 dpavlin 12 uint64_t dev_dyntrans_write_low[MAX_DEVICES];
79     uint64_t dev_dyntrans_write_high[MAX_DEVICES];
80    
81 dpavlin 20 int dev_dyntrans_alignment;
82 dpavlin 12
83 dpavlin 20
84 dpavlin 4 /*
85 dpavlin 12 * NOTE/TODO: This bintrans was for MIPS only. Ugly. :-/
86     */
87    
88     /*
89 dpavlin 4 * translation_code_chunk_space is a large chunk of (linear) memory
90     * where translated code chunks and translation_entrys are stored.
91     * When this is filled, translation is restart from scratch (by
92     * resetting translation_code_chunk_space_head to 0, and removing all
93     * translation entries).
94     *
95     * (Using a static memory region like this is somewhat inspired by
96     * the QEMU web pages,
97     * http://fabrice.bellard.free.fr/qemu/qemu-tech.html#SEC13)
98     */
99    
100     unsigned char *translation_code_chunk_space;
101     size_t translation_code_chunk_space_head;
102    
103     int bintrans_32bit_only;
104    
105     struct translation_page_entry **translation_page_entry_array;
106    
107     unsigned char *quick_jump_host_address[MAX_QUICK_JUMPS];
108     int quick_jump_page_offset[MAX_QUICK_JUMPS];
109     int n_quick_jumps;
110     int quick_jumps_index;
111     };
112    
113     #define BITS_PER_PAGETABLE 20
114     #define BITS_PER_MEMBLOCK 20
115     #define MAX_BITS 40
116    
117    
118     /* memory.c: */
119 dpavlin 20 #define MEM_PCI_LITTLE_ENDIAN 128
120 dpavlin 4 uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len);
121     void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,
122     uint64_t data);
123    
124     void *zeroed_alloc(size_t s);
125    
126 dpavlin 12 struct memory *memory_new(uint64_t physical_max, int arch);
127 dpavlin 4
128     int memory_points_to_string(struct cpu *cpu, struct memory *mem,
129     uint64_t addr, int min_string_length);
130     char *memory_conv_to_string(struct cpu *cpu, struct memory *mem,
131     uint64_t addr, char *buf, int bufsize);
132    
133     unsigned char *memory_paddr_to_hostaddr(struct memory *mem,
134     uint64_t paddr, int writeflag);
135    
136     /* memory_fast_v2h.c: */
137     unsigned char *fast_vaddr_to_hostaddr(struct cpu *cpu, uint64_t vaddr,
138     int writeflag);
139    
140 dpavlin 6 /* MIPS stuff: */
141 dpavlin 4 int translate_address_mmu3k(struct cpu *cpu, uint64_t vaddr,
142     uint64_t *return_addr, int flags);
143     int translate_address_mmu8k(struct cpu *cpu, uint64_t vaddr,
144     uint64_t *return_addr, int flags);
145     int translate_address_mmu10k(struct cpu *cpu, uint64_t vaddr,
146     uint64_t *return_addr, int flags);
147     int translate_address_mmu4100(struct cpu *cpu, uint64_t vaddr,
148     uint64_t *return_addr, int flags);
149     int translate_address_generic(struct cpu *cpu, uint64_t vaddr,
150     uint64_t *return_addr, int flags);
151    
152 dpavlin 6
153 dpavlin 20 /* Writeflag: */
154     #define MEM_READ 0
155     #define MEM_WRITE 1
156     #define MEM_DOWNGRADE 128
157    
158     /* Misc. flags: */
159     #define CACHE_DATA 0
160     #define CACHE_INSTRUCTION 1
161     #define CACHE_NONE 2
162     #define CACHE_FLAGS_MASK 0x3
163     #define NO_EXCEPTIONS 16
164     #define PHYSICAL 32
165     #define NO_SEGMENTATION 64 /* for X86 */
166     #define MEMORY_USER_ACCESS 128 /* for ARM, at least */
167    
168     /* Dyntrans Memory flags: */
169     #define DM_DEFAULT 0
170     #define DM_DYNTRANS_OK 1
171     #define DM_DYNTRANS_WRITE_OK 2
172     #define DM_READS_HAVE_NO_SIDE_EFFECTS 4
173     #define DM_EMULATED_RAM 8
174    
175 dpavlin 4 #define FLAG_WRITEFLAG 1
176     #define FLAG_NOEXCEPTIONS 2
177     #define FLAG_INSTR 4
178    
179     int userland_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
180     unsigned char *data, size_t len, int writeflag, int cache);
181 dpavlin 18 #define MEMORY_ACCESS_FAILED 0
182     #define MEMORY_ACCESS_OK 1
183     #define MEMORY_ACCESS_OK_WRITE 2
184     #define MEMORY_NOT_FULL_PAGE 256
185 dpavlin 4
186 dpavlin 12 void memory_device_dyntrans_access(struct cpu *, struct memory *mem,
187 dpavlin 4 void *extra, uint64_t *low, uint64_t *high);
188    
189     void memory_device_register_statefunction(
190     struct memory *mem, void *extra,
191     int (*dev_f_state)(struct cpu *,
192     struct memory *, void *extra, int wf, int nr,
193     int *type, char **namep, void **data, size_t *len));
194    
195     void memory_device_register(struct memory *mem, const char *,
196     uint64_t baseaddr, uint64_t len, int (*f)(struct cpu *,
197     struct memory *,uint64_t,unsigned char *,size_t,int,void *),
198 dpavlin 12 void *extra, int flags, unsigned char *dyntrans_data);
199 dpavlin 4 void memory_device_remove(struct memory *mem, int i);
200    
201     #endif /* MEMORY_H */
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