/[gxemul]/trunk/src/include/memory.h
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Revision 12 - (hide annotations)
Mon Oct 8 16:18:38 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 6520 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 dpavlin 4 #ifndef MEMORY_H
2     #define MEMORY_H
3    
4     /*
5     * Copyright (C) 2004-2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 12 * $Id: memory.h,v 1.35 2005/07/19 10:48:07 debug Exp $
32 dpavlin 4 *
33     * Memory controller related functions.
34     */
35    
36     #include <sys/types.h>
37     #include <inttypes.h>
38    
39     #include "misc.h"
40    
41    
42     #define DEFAULT_RAM_IN_MB 32
43     #define MAX_DEVICES 24
44    
45     #define DEVICE_STATE_TYPE_INT 1
46     #define DEVICE_STATE_TYPE_UINT64_T 2
47    
48     struct cpu;
49     struct translation_page_entry;
50    
51     /* For bintrans: */
52     #define MAX_QUICK_JUMPS 8
53    
54     struct memory {
55     uint64_t physical_max;
56     void *pagetable;
57    
58     int n_mmapped_devices;
59     int last_accessed_device;
60     /* The following two might speed up things a little bit. */
61     /* (actually maxaddr is the addr after the last address) */
62     uint64_t mmap_dev_minaddr;
63     uint64_t mmap_dev_maxaddr;
64    
65     const char *dev_name[MAX_DEVICES];
66     uint64_t dev_baseaddr[MAX_DEVICES];
67     uint64_t dev_length[MAX_DEVICES];
68     int dev_flags[MAX_DEVICES];
69     void *dev_extra[MAX_DEVICES];
70     int (*dev_f[MAX_DEVICES])(struct cpu *,struct memory *,
71     uint64_t,unsigned char *,size_t,int,void *);
72     int (*dev_f_state[MAX_DEVICES])(struct cpu *,
73     struct memory *, void *extra, int wf, int nr,
74     int *type, char **namep, void **data, size_t *len);
75 dpavlin 12 unsigned char *dev_dyntrans_data[MAX_DEVICES];
76 dpavlin 4
77 dpavlin 12 int dev_dyntrans_alignment;
78 dpavlin 4
79 dpavlin 12 uint64_t dev_dyntrans_write_low[MAX_DEVICES];
80     uint64_t dev_dyntrans_write_high[MAX_DEVICES];
81    
82    
83 dpavlin 4 /*
84 dpavlin 12 * NOTE/TODO: This bintrans was for MIPS only. Ugly. :-/
85     */
86    
87     /*
88 dpavlin 4 * translation_code_chunk_space is a large chunk of (linear) memory
89     * where translated code chunks and translation_entrys are stored.
90     * When this is filled, translation is restart from scratch (by
91     * resetting translation_code_chunk_space_head to 0, and removing all
92     * translation entries).
93     *
94     * (Using a static memory region like this is somewhat inspired by
95     * the QEMU web pages,
96     * http://fabrice.bellard.free.fr/qemu/qemu-tech.html#SEC13)
97     */
98    
99     unsigned char *translation_code_chunk_space;
100     size_t translation_code_chunk_space_head;
101    
102     int bintrans_32bit_only;
103    
104     struct translation_page_entry **translation_page_entry_array;
105    
106     unsigned char *quick_jump_host_address[MAX_QUICK_JUMPS];
107     int quick_jump_page_offset[MAX_QUICK_JUMPS];
108     int n_quick_jumps;
109     int quick_jumps_index;
110     };
111    
112     #define BITS_PER_PAGETABLE 20
113     #define BITS_PER_MEMBLOCK 20
114     #define MAX_BITS 40
115    
116     #define MEM_READ 0
117     #define MEM_WRITE 1
118    
119    
120     #define CACHE_DATA 0
121     #define CACHE_INSTRUCTION 1
122     #define CACHE_NONE 2
123    
124     #define CACHE_FLAGS_MASK 0x3
125    
126 dpavlin 6 #define NO_EXCEPTIONS 16
127     #define PHYSICAL 32
128     #define NO_SEGMENTATION 64 /* for X86 */
129 dpavlin 4
130    
131     /* memory.c: */
132     uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len);
133     void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,
134     uint64_t data);
135    
136     void *zeroed_alloc(size_t s);
137    
138 dpavlin 12 struct memory *memory_new(uint64_t physical_max, int arch);
139 dpavlin 4
140     int memory_points_to_string(struct cpu *cpu, struct memory *mem,
141     uint64_t addr, int min_string_length);
142     char *memory_conv_to_string(struct cpu *cpu, struct memory *mem,
143     uint64_t addr, char *buf, int bufsize);
144    
145     unsigned char *memory_paddr_to_hostaddr(struct memory *mem,
146     uint64_t paddr, int writeflag);
147    
148     /* memory_fast_v2h.c: */
149     unsigned char *fast_vaddr_to_hostaddr(struct cpu *cpu, uint64_t vaddr,
150     int writeflag);
151    
152 dpavlin 6 /* MIPS stuff: */
153 dpavlin 4 int translate_address_mmu3k(struct cpu *cpu, uint64_t vaddr,
154     uint64_t *return_addr, int flags);
155     int translate_address_mmu8k(struct cpu *cpu, uint64_t vaddr,
156     uint64_t *return_addr, int flags);
157     int translate_address_mmu10k(struct cpu *cpu, uint64_t vaddr,
158     uint64_t *return_addr, int flags);
159     int translate_address_mmu4100(struct cpu *cpu, uint64_t vaddr,
160     uint64_t *return_addr, int flags);
161     int translate_address_generic(struct cpu *cpu, uint64_t vaddr,
162     uint64_t *return_addr, int flags);
163    
164 dpavlin 6 /* X86 stuff: */
165     int translate_address_x86(struct cpu *cpu, uint64_t vaddr,
166     uint64_t *return_addr, int flags);
167    
168    
169 dpavlin 4 #define FLAG_WRITEFLAG 1
170     #define FLAG_NOEXCEPTIONS 2
171     #define FLAG_INSTR 4
172    
173     int userland_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
174     unsigned char *data, size_t len, int writeflag, int cache);
175     #define MEMORY_ACCESS_FAILED 0
176     #define MEMORY_ACCESS_OK 1
177    
178 dpavlin 12 void memory_device_dyntrans_access(struct cpu *, struct memory *mem,
179 dpavlin 4 void *extra, uint64_t *low, uint64_t *high);
180    
181     void memory_device_register_statefunction(
182     struct memory *mem, void *extra,
183     int (*dev_f_state)(struct cpu *,
184     struct memory *, void *extra, int wf, int nr,
185     int *type, char **namep, void **data, size_t *len));
186    
187     void memory_device_register(struct memory *mem, const char *,
188     uint64_t baseaddr, uint64_t len, int (*f)(struct cpu *,
189     struct memory *,uint64_t,unsigned char *,size_t,int,void *),
190 dpavlin 12 void *extra, int flags, unsigned char *dyntrans_data);
191 dpavlin 4 void memory_device_remove(struct memory *mem, int i);
192    
193 dpavlin 6 /* Bit flags: */
194     #define MEM_DEFAULT 0
195 dpavlin 12 #define MEM_DYNTRANS_OK 1
196     #define MEM_DYNTRANS_WRITE_OK 2
197 dpavlin 6 #define MEM_READING_HAS_NO_SIDE_EFFECTS 4
198 dpavlin 4
199    
200     #endif /* MEMORY_H */

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